A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme

Tanaka, Hitoshi; Aoki, Masakazu; Sakata, T.; Kimura, S.; Sakashita, N.; Hidaka, Hideto; Tachibana, T.; Kimura, K.

doi:10.1109/4.777106

Cited by 50 publications

(14 citation statements)

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“…T ODAY, there is an increased demand for the use of multiple voltage levels in various semiconductor circuits like nonvolatile memories [1]- [3], dynamic [4]- [6] and static [7], [8] random access memories, and low-power [9]- [11], and lowvoltage [12] circuits. High voltages, above the nominal technology voltage, and negative voltages are widely used in circuit operation along with the nominal power supply voltage .…”

Section: Introductionmentioning

confidence: 99%

“…For that reason, level-conversion circuits, which convert a voltage-level signal into another voltage-level signal, are required for the proper interconnection between blocks with different operating voltages. Since negative voltages are exploited in many circuit operations (Flash memory erase operation [3], [13], DRAM refresh time enhancement [4], [5], low standby power consumption mode activation [7]- [9], ESD protection [14], and circuit calibration [15], [16]), converters that can treat negative voltages are of great importance.…”

Section: Introductionmentioning

confidence: 99%

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A Stress-Relaxed Negative Voltage-Level Converter

Tsiatouhas

2007

IEEE Trans. Circuits Syst. II

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In this brief, a new embedded negative voltage-level converter (level shifter) is presented. The proposed circuit can convert a positive input signal to a negative output signal with reduced or even without (depending on the application) voltage stress on the used MOS devices. The circuit has been designed in a 0.18-m triple-well standard CMOS technology, using double-gate-oxidethickness MOS transistors with an absolute maximum rating of 4.0 V, a nominal power supply of 1.8 V, and a required negative voltage of 3.3 V. Simulation results are provided to demonstrate the efficiency of the proposed topology. According to the results, 1.82-ns delay and 0.53-mW power consumption are reported. Index Terms-Embedded negative voltage-level converter, level shifter, level conversion, MOS-device voltage stress relaxation.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Stress-Relaxed Negative Voltage-Level Converter

Tsiatouhas

2007

IEEE Trans. Circuits Syst. II

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“…Introduction: In the DRAM industry, the negative word line (NWL) scheme [1] is presently one of the most representative techniques used for low voltage operation [2][3][4]. However, it also has disadvantages, such as gate-induced drain leakage (GIDL) [5].…”

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confidence: 99%

Selective negative word line scheme for improving refresh

Lee¹,

Park²,

Ahn³

2011

Electron. Lett.

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Proposed is a new selective negative word line scheme that yields almost 2.7% of the fail bit count (FBC) in a DRAM chip with a conventional negative word line scheme in the pause refresh state. It has a superior dynamic refresh characteristic, which is almost 0.3% of the FBC in a DRAM chip using the ground word line scheme. This scheme leads to a very low cell V TH (threshold voltage).Introduction: In the DRAM industry, the negative word line (NWL) scheme [1] is presently one of the most representative techniques used for low voltage operation [2][3][4]. However, it also has disadvantages, such as gate-induced drain leakage (GIDL) [5]. We propose a new NWL approach called the 'selective negative word line scheme' (SNWL) [6], which has the advantages of both the conventional NWL and the ground word line (GWL) scheme, even though it has an area penalty of 0.01% for the switching circuits, compared with the NWL scheme.

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“…Basic cores of precision circuits are voltage and current references which are required to provide stable electrical reference points independent of temperature, supply voltage and load [3,4,5].…”

Section: Introductionmentioning

confidence: 99%