A predictive synchronizer for periodic clock domains

Frank, Uri; Kapshitz, Tsachy; Ginosar, Ran

doi:10.1007/s10703-006-7843-9

Cited by 16 publications

(4 citation statements)

References 14 publications

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“…Arbitration is therefore necessary to ensure that the token is passed between the configurations without incident. This is similar to prior work used to arbitrate between the configurations in a system with plausible clocks [16]. It also shares commonalities with prior work on lazy-ring arbiters [17].…”

Section: Reconfiguration Protocolsupporting

confidence: 64%

Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging

Guido

Yakovlev

2015

IEEE Trans. VLSI Syst.

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Synchronization is an important issue in modern system design as systems-on-chips integrate more diverse technologies, operating voltages, and clock frequencies on a single substrate. This paper presents a methodology for the design and implementation of a self-timed reconfigurable control device suitable for a parallel cascaded flip-flop synchronizer based on a principle known as wagging, through the application of distributed feedback graphs. By modifying the endpoint adjacency of a common behavior graph via one-hot codes, several configurable modes can be implemented in a single design specification, thereby facilitating direct control over the synchronization time and the mean-time between failures of the parallel master-slave latches in the synchronizer. Therefore, the resulting implementation is resistant to process nonidealities, which are present in physical design layouts. This paper includes a discussion of the reconfiguration protocol, and implementations of both a sequential token ring control device, and an interrupt subsystem necessary for reconfiguration, all simulated in UMC 90-nm technology. The interrupt subsystem demonstrates operating frequencies between 505 and 818 MHz per module, with average power consumptions between 70.7 and 90.0 µW in the typical-typical case under a corner analysis.

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Section: Reconfiguration Protocolsupporting

confidence: 64%

Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging

Guido

Yakovlev

2015

IEEE Trans. VLSI Syst.

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“…Another possibility that has been exploited in previous synchronizer designs is a relationship between the clock frequencies. If the clocks are available to the synchronizer and are periodic it is possible to create a circuit to predict timing conflicts before they occur even if the frequencies are different [29]. This is accomplished by creating fast forwarded versions of the clocks and then comparing those in advance.…”

Section: Synchronizers For Systems With Known Frequency Differencesmentioning

confidence: 99%

Gradual Synchronization

Jackson¹,

Manohar

2016

2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

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Comparison of the MTBF of several synchronizer configurations. The flip-flop synchronizers shown are for N=2 meaning about one clock cycle is allotted for metastability resolution.. .. .. . 4.5 Comparison of the MTBF of several synchronizer configurations. The flip-flop synchronizers shown are for N=1.5 meaning about half a clock cycle is allotted for metastability resolution.. .. .. 4.6 Comparison of the MTBF of a 4-phase gradual synchronizer with varying numbers of stages on the request and acknowledge ends. 4.7 Worst case forward latency comparison of the synchronizers.. .

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“…26 Ginosar described synchronizer errors and misperceptions. 27 Frank et al 28 and Dobkin et al 29 presented examples of formal synchronizer verification. Finally, Beigné et al discussed employing a NoC to solve all synchronization issues.…”

Section: Literature Resources On Metastabilitymentioning

confidence: 99%

Metastability and Synchronizers: A Tutorial

Ginosar¹

2011

IEEE Des. Test. Comput.

121

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METASTABILITY EVENTS ARE common in digital circuits, and synchronizers are a necessity to protect us from their fatal effects. Originally, synchronizers were required when reading an asynchronous input (that is, an input not synchronized with the clock so that it might change exactly when sampled). Now, with multiple clock domains on the same chip, synchronizers are required when on-chip data crosses the clock domain boundaries. Any flip-flop can easily be made metastable. Toggle its data input simultaneously with the sampling edge of the clock, and you get metastability. One common way to demonstrate metastability is to supply two clocks that differ very slightly in frequency to the data and clock inputs. During every cycle, the relative time of the two signals changes a bit, and eventually they switch sufficiently close to each other, leading to metastability. This coincidence happens repeatedly, enabling demonstration of metastability with normal instruments. Understanding metastability and the correct design of synchronizers to prevent it is sometimes an art. Stories of malfunction and bad synchronizers are legion. Synchronizers cannot always be synthesized, they are hard to verify, and often what has been good in the past may be bad in the future. Papers, patents, and application notes giving wrong instructions are too numerous, as well as library elements and IP cores from reputable sources that might be ''unsafe at any speed.'' This article offers a glimpse into the theory and practice of metastability and synchronizers; the sidebar ''Literature Resources on Metastability'' provides a short list of resources where you can learn more about this subject.

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A predictive synchronizer for periodic clock domains

Cited by 16 publications

References 14 publications

Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging

Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging

Gradual Synchronization

Metastability and Synchronizers: A Tutorial

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