A Predictor-Based Power-Saving Policy for DRAM Memories

Abstract

Abstract-Reducing power/energy consumption is an important goal for all computer systems, from servers to battery-driven hand-held devices. To achieve this goal, the energy consumption of all system components needs to be reduced. One of the most power-hungry components is the off-chip DRAM, even when it is idle. DRAMs support different power-saving modes, such as self-refresh and power-down, but employing them every time the DRAM is idle, reduces performance due to their power-up latencies. The self-refresh mode offers large power savings, but incurs a long power-up latency. The power-down mode, on the other hand, has a shorter power-up latency, but provides lower power savings.In this paper, we propose and evaluate a novel power-saving policy that combines the best of both power-saving modes in order to achieve significant power reductions with a marginal performance penalty. To accomplish this, we use a history-based predictor to forecast the duration of an idle period and then either employ self-refresh, or power-down, or a combination of both power saving modes. Significant refinements are made to the predictor to maximize the energy savings and minimize the performance penalty. The presented policy is evaluated using several applications from the multimedia domain and the experimental results show that it reduces the total DRAM energy consumption between 68.8% and 79.9% at a negligible performance penalty between 0.3% and 2.2%.

A generic implementation of a quantified predictor on FPGAs

“…The authors in [5] presented a fuzzy logic controller running on an FPGA. This controller used a similar technique like [15] and [14] to forecast data points. In [7] the authors presented an implementation of intelligent predictors for solar irradiation running on FPGA.…”

“…In [15], a predictor was applied to forecast traffic in NoC, however the authors presented only results based on a software implementation. In [14], the same predictor was used inside a memory controller to snoop memory access. With this data, the predictor forecasts memory idle periods and based on this forecasts a power-saving policy was presented to achieve significant power reductions with only a marginal performance penalty.…”

“…(2) A complete scalability analysis for the RTL implementation of the generic predictor is presented, which includes resource, frequency and power consumption analysis for a field programmable gate array (FPGA). (3) We evaluate the hardware predictor by applying the power-saving policy presented in [14]. This shows the efficiency of this policy by predicting the memory idle periods for three different multimedia benchmarks including the power consumption of the predictor itself This paper is organized as follows: Section 2 presents a brief overview of related work.…”

“…The VHDL implementation of the predictor is described in Section 4 including the whole data path as well as the control unit. Section 5 depicts the complexity, frequency and power consumption analysis as well as the evaluation of the power-saving policy from [14]. Finally, Section 6 summarizes and highlights the contributions of this work.…”

“…These types of predictors allow developing of strategies and policies that can increase system performance or reduce power consumption. For example, in [14] a power-saving policy was presented that reduces the dynamic random-access memory (DRAM) power consumption tremendously. The whole power-saving policy is based on a predictor which forecasts the length of the memory idle periods.…”