A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications

Chang, Ik Joon; Mohapatra, D.; Roy, Kaushik

doi:10.1109/tcsvt.2011.2105550

Cited by 118 publications

(81 citation statements)

References 7 publications

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“…A similar idea is proposed in [18] where least-significantbits (LSB) of each word is stored in an error-prone but areaefficient 6T SRAM. Occasional bit-errors at low voltages are tolerable for its target application as these errors are limited to the LSB of each word.…”

Section: A Application-specific Sram Designsmentioning

confidence: 99%

Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9$\times$ Lower Energy/Access

Sinangil

Chandrakasan

2014

IEEE J. Solid-State Circuits

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Abstract-This paper presents an application-specific SRAM design targeted towards applications with highly correlated data (e.g. video and imaging applications). A prediction-based reduced bit-line switching activity scheme is proposed to reduce switching activity on the bit-lines based on the proposed bit-cell and array structure. A statistically gated sense-amplifier approach is used to exploit signal statistics on the bit-lines to reduce energy consumption of the sensing network. These techniques provide up to 1.9× lower energy/access when compared to an 8T SRAM. These savings are in addition to the savings that are achieved through voltage scaling and demonstrate the advantages of an application-specific SRAM design.

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Section: A Application-specific Sram Designsmentioning

confidence: 99%

Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9$\times$ Lower Energy/Access

Sinangil

Chandrakasan

2014

IEEE J. Solid-State Circuits

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“…Fig. 3 depicts the failure probability of a memory array implemented by medium-sized 6T bit-cells, 15% upsized 6T cells and 8T bit-cells under various voltages in case of slow-fast corner, which was found to be the worst corner for RDF induced memory failures in the 65nm technology node [5,9]. Such failure rates are directly related to the yield of a memory block.…”

Section: Hardware Errors and Impact On Yield And Memory Operationmentioning

confidence: 99%

“…Note that for the implementation of such a hybrid memory we could also utilize upsized 6T cells for the protection of the required bits. However, it was shown recently that 8T cells lead to lower area and power overhead for the same stability improvement [9]. In any case, the same techniques applied in the design of such a hybrid memory for multimedia applications [9] can be utilized also here.…”

Section: Efficiency Of Protectionmentioning

confidence: 99%

“…Interestingly, as the percentage of memory components in wireless systems increases (crucial for supporting the large data load), the overhead of such techniques makes them prohibitive, reducing their viability. For instance, error correction coding (ECC) and novel bit-cell architectures (i.e., 8T) might tackle the high failure probability of traditional 6 transistor (6T) bit-cells (under variations and VS) but can lead to more than 50% power overhead [5][6][7][8][9]. However, although in general purpose processors/systems the overhead of such techniques might still be acceptable due to the equal significance of all data, it might be possible in application-specific systems to depart from the 100% error-free computing paradigm.…”

Section: Introductionmentioning

confidence: 99%

“…By accepting dies even with a number of defects or restricting application of robust techniques to only the most critical parts of the system we could improve yield and energy efficiency at no/limited overhead even in the presence of hardware errors (due to VS and/or variations). While several approaches tried to take advantage of such an observation in order to address the issues of power and variations in multimedia systems and individual DSP blocks [2,8,9], to the best or our knowledge, no such effort has targeted wireless communication systems so far. Therefore, there is a need to study the impact of hardware errors induced by parametric variations and VS on the performance of such systems, which are ubiquitous components of all today's portable devices.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

On the exploitation of the inherent error resilience of wireless systems under unreliable silicon

Karakonstantis

Roth

Benkeser

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

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In this paper, we investigate the impact of circuit misbehavior due to parametric variations and voltage scaling on the performance of wireless communication systems. Our study reveals the inherent error resilience of such systems and argues that sufficiently reliable operation can be maintained even in the presence of unreliable circuits and manufacturing defects. We further show how selective application of more robust circuit design techniques is sufficient to deal with high defect rates at low overhead and improve energy efficiency with negligible system performance degradation.

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RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience

Herkersdorf

Engel

Glaß

et al. 2020

Dependable Embedded Systems

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The Resilience Articulation Point (RAP) model aims to provision a probabilistic fault abstraction and error propagation concept for various forms of variability related faults in deep sub-micron CMOS technologies at the semiconductor material or device levels. RAP assumes that each of such physical faults will eventually manifest as a single- or multi-bit binary signal inversion or out-of-specification delay in a signal transition between bit values. When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, finite state machine (FSM) states, IP macro-interfaces, or software variables. Thus, design concerns can be investigated at higher abstraction layers without the necessity to further consider the full details of lower levels of design. This chapter introduces the ideas of RAP based on examples of particle strike, noise and voltage drop induced bit errors in SRAM cells. Furthermore, we show by different examples how probabilistic bit flips are systematically abstracted and propagated towards instruction and data vulnerability at MPSoC architecture level, and how RAP can be applied for dynamic testing and application-level optimizations in an autonomous robot scenario.

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A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications

Cited by 118 publications

References 7 publications

Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9$\times$ Lower Energy/Access

Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9$\times$ Lower Energy/Access

On the exploitation of the inherent error resilience of wireless systems under unreliable silicon

RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience

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