Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9$\times$ Lower Energy/Access

Sinangil, Mahmut E.; Chandrakasan, Anantha P.

doi:10.1109/jssc.2013.2280310

Cited by 46 publications

(18 citation statements)

References 18 publications

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“…E array is the dominant component of energy consumption in high-density SRAMs during normal read operations [3], [8], [25]. Hence, we focus on E array , which is given by…”

Section: Sram Metrics For Resource and Fidelitymentioning

confidence: 99%

Generalized Water-filling for Source-aware Energy-efficient SRAMs

Kim

Kang

Varshney

et al. 2018

IEEE Trans. Commun.

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Conventional low-power static random access memories (SRAMs) reduce read energy by decreasing the bit-line voltage swings uniformly across the bit-line columns. This is because the read energy is proportional to the bit-line swings. On the other hand, bit-line swings are limited by the need to avoid decision errors especially in the most significant bits. We propose a principled approach to determine optimal non-uniform bit-line swings by formulating convex optimization problems. For a given constraint on mean squared error of retrieved words, we consider criteria to minimize energy (for low-power SRAMs), maximize speed (for high-speed SRAMs), and minimize energy-delay product.These optimization problems can be interpreted as classical water-filling, ground-flattening and waterfilling, and sand-pouring and water-filling, respectively. By leveraging these interpretations, we also propose greedy algorithms to obtain optimized discrete swings. Numerical results show that energyoptimal swing assignment reduces energy consumption by half at a peak signal-to-noise ratio of 30dB for an 8-bit accessed word. The energy savings increase to four times for a 16-bit accessed word. I. INTRODUCTIONVon Neumann computing architectures separate memory units from computing units so there is frequent data access that consumes enormous energy. Since static random access memories (SRAMs) access requires more energy than arithmetic operations [1], SRAM access energy accounts for the significant part of the total energy consumption in many information processing This work was supported in part by Systems on Nanoscale Information fabriCs (SONIC), one of the six SRC STARnet Centers, sponsored by MARCO and DARPA. arXiv:1710.07153v3 [cs.IT] 29 Nov 2017 formulate convex optimization problems whose objectives are as follows: C1. Minimize energy (low-power SRAMs), C2. Maximize speed (high-speed SRAMs), C3. Minimize energy-delay product (EDP).Solutions to these convex problems yield optimal performance that is theoretically attainable.By casting read access for SRAMs as communication over parallel channels, we investigate the fundamental trade-offs between physical resources (energy, delay, and EDP) and a fidelity (MSE) constraint.In addition, we provide generalized water-filling interpretations for our optimal solutions. This follows since accessing a B-bit word is equivalent to communicating information through B parallel channels. In classical water-filling, the ground represents the noise levels of parallel channels [20], [21]. On the other hand, the importance of each bit position determines the ground level in our optimization problems. Each optimization problem has its own interpretation depending on its objective function: water-filling (C1), ground-flattening and water-filling (C2), and sand-pouring and water-filling (C3), respectively. We also observe interesting connections between our problems and variants on water-filling such as constant-power water-filling [22],[23] and mercury/water-filling [24]. Also, we show that the proposed ...

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“…E array is the dominant component of energy consumption in high-density SRAMs during normal read operations [3], [8], [25]. Hence, we focus on E array , which is given by…”

Section: Sram Metrics For Resource and Fidelitymentioning

confidence: 99%

Generalized Water-filling for Source-aware Energy-efficient SRAMs

Kim

Kang

Varshney

et al. 2018

IEEE Trans. Commun.

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“…During read, BL(BLB) discharges through the cell, while BLB(BL) stays at V DD . BL switching can account for more than half of total read power [3]. For the write operation, one of the BLs is discharged through write driver.…”

Section: Existing Implementationsmentioning

confidence: 99%

Charge sharing based 10T SRAM for low-power

Maroof

Sohail

Shin

2016

IEICE Electron. Express

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We propose a novel charge sharing bit-line 10T SRAM for differential read and single ended (SE) write. Decoupled read provides high noise margin. Read bit-lines are not charged to full V DD , and these share charge for read 1 operation. A new write driver is proposed for SE write which charges the write-bit-line conditionally. Virtual power rail is used to suppress bit-line leakages. Compared with 6T SRAM, charge sharing scheme potentially consumes only 25% read and 50% write dynamic power. Thorough comparisons with 6T at 45 nm node show that the proposed 10T design has 2× read static noise margin, 71% reduction in total read and 48% reduction in total write power.

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“…In certain capacities, these latch arrays can be area-competitive with SRAMs as SRAMs typically require additional support circuitry [31]. Second, we are investigating read-assist and write-assist circuits that enable SRAMs to operate at voltages below their natural stability point [32], [33].…”

Section: Reduced-voltage Operationmentioning

confidence: 99%

Scaling the Power Wall: A Path to Exascale

Villa

Johnson

O'Connor³

et al. 2014

SC14: International Conference for High Performance Computing, Networking, Storage and Analysis

100

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Abstract-Modern scientific discovery is driven by an insatiable demand for computing performance. The HPC community is targeting development of supercomputers able to sustain 1 ExaFlops by the year 2020 and power consumption is the primary obstacle to achieving this goal. A combination of architectural improvements, circuit design, and manufacturing technologies must provide over a 20× improvement in energy efficiency. In this paper, we present some of the progress NVIDIA Research is making toward the design of Exascale systems by tailoring features to address the scaling challenges of performance and energy efficiency. We evaluate several architectural concepts for a set of HPC applications demonstrating expected energy efficiency improvements resulting from circuit and packaging innovations such as low-voltage SRAM, low-energy signaling, and on-package memory. Finally, we discuss the scaling of these features with respect to future process technologies and provide power and performance projections for our Exascale research architecture.

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Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9$\times$ Lower Energy/Access

Cited by 46 publications

References 18 publications

Generalized Water-filling for Source-aware Energy-efficient SRAMs

Generalized Water-filling for Source-aware Energy-efficient SRAMs

Charge sharing based 10T SRAM for low-power

Scaling the Power Wall: A Path to Exascale

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