A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime

Abstract

Microarchitectural redundancy has been proposed as a means of improving chip lifetime reliability. It is typically used in a reactive way, allowing chips to maintain operability in the presence of failures by detecting and isolating, correcting, and/or replacing components on a first-come, first-served basis only after they become faulty. In this paper, we explore an alternative, more preferred method of exploiting microarchitectural redundancy to enhance chip lifetime reliability. In our proposed approach, redundancy is used proactively to allow non-faulty microarchitecture components to be temporarily deactivated, on a rotating basis, to suspend and/or recover from certain wearout effects. This approach improves chip lifetime reliability by warding off the onset of wearout failures as opposed to reacting to them posteriorly. Applied to on-chip cache SRAM for combating NBTI-induced wearout failure, our proactive wearout recovery approach increases lifetime reliability (measured in mean-time-to-failure) of the cache by about a factor of seven relative to no use of microarchitectural redundancy and a factor of five relative to conventional reactive use of redundancy having similar area overhead.

Modeling and Experimental Demonstration of Accelerated Self-Healing Techniques

“…Here we distinguish between passive recovery (system unstressed when not in use) and active recovery (proactively scheduled accelerated recovery periods) similar to [14], and make the claim that passive recovery, by being slow, and unpredictable, cannot effectively be used to improve metrics and reduce margins; thus it is sometimes even ignored when modeling aging phenomena. Recovery can be made active by reversing the direction of the stress (e.g.…”

Mitigating NBTI Degradation on FinFET GPUs through Exploiting Device Heterogeneity

“…Gunadi et al [22] introduce a scheme called Colt to balance the utilization of devices in a processor for reliability improvement. Specifically focusing on the storage components, Shin et al [35] propose to proactively set the PMOS transistors to recovery mode, and moving data around free cache arrays during operation. Converse to these works which attempt to manipulate the time under stress and recovery, Tiwari et al [38] propose a framework named facelift to combat NBTI degradation by adjusting higher level parameters including operating voltage, threshold voltage and the application scheduling policy.…”

Energy-optimal caches with guaranteed lifetime

“…The work of [12] introduces a dynamic indexing scheme in which the cache indexing function is modified over time in order to achieve a uniform distribution of idleness over the cache lines; in this way all the leakage saving opportunities can also be used for aging reduction. One architectural approach based on redundancy is the one proposed in [14], in which a spare cache sub-array is used to replace, on a rotating basis, selected sub-arrays with excessive aging, which are then put into a special wearoutrecovery state implemented through a sort of power gating. This approach is more fine-grain than ours, but requires considerable overhead.…”