A Programmable 10b up-to-6MS/s SAR-ADC Featuring Constant-FoM with On-Chip Reference Voltage Buffers

Borghetti, F.; Nielsen, J.H.; Ferragina, V.; Malcovati, P.; Andreani, Pietro; Basçhirotto, A.

doi:10.1109/esscir.2006.307499

Cited by 14 publications

(15 citation statements)

References 3 publications

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“…Majority of the publications on SAR ADCs do not incorporate on-chip RVBuffers. In the works on SAR ADCs which include RVBuffers, attention is drawn mostly to the dominant power consumption of the block while other important design metrics are not discussed in-depth [107], [12]. This work discusses the comprehensive performance requirements on the RVBuffer, coarse estimation of design parameters and choice of a suitable amplifier topology.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Although SAR ADCs have been the subject of intense research in recent years, scant attention has been laid on the design of high-performance on-chip RVBuffers. The few existing works [12] emphasize only the dominant power consumption of the buffer. The estimation of important design parameters of the buffer as well critical specifications such as PSRR, output noise, offset, settling time and stability have been elaborated upon in this dissertation.…”

Section: Methodsmentioning

confidence: 99%

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Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Harikumar¹

2016

Linköping Studies in Science and Technology. Dissertations

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Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless sensor networks (WSNs), wireless/wireline communication receivers and data acquisition systems. To achieve long-term, autonomous operation for WSNs, the nodes are powered by harvesting energy from ambient sources such as solar energy, vibrational energy etc. Since the signal frequencies in these distributed WSNs are often low, ultra-low-power ADCs with low sampling rates are required. The advent of new wireless standards with ever-increasing data rates and bandwidth necessitates ADCs capable of meeting the demands. Wireless standards such as GSM, GPRS, LTE and WLAN require ADCs with several tens of MS/s speed and moderate resolution (8-10 bits). Since these ADCs are incorporated into battery-powered portable devices such as cellphones and tablets, low power consumption for the ADCs is essential.The first contribution is an ultra-low-power 8-bit, 1 kS/s successive approximation register (SAR) ADC that has been designed and fabricated in a 65-nm CMOS process. The target application for the ADC is an autonomously-powered soil-moisture sensor node. At V DD = 0.4 V, the ADC consumes 717 pW and achieves an FoM = 3.19 fJ/conv-step while meeting the targeted dynamic and static performance. The 8-bit ADC features a leakage-suppressed S/H circuit with boosted control voltage which achieves > 9-bit linearity. A binary-weighted capacitive array digital-to-analog converter (DAC) is employed with a very low, custom-designed unit capacitor of 1.9 fF. Consequently the area of the ADC and power consumption are reduced. The ADC achieves an ENOB of 7.81 bits at near-Nyquist input frequency. The core area occupied by the ADC is only 0.0126 mm 2 .The second contribution is a 1.2 V, 10 bit, 50 MS/s SAR ADC designed and implemented in 65 nm CMOS aimed at communication applications. For medium-tohigh sampling rates, the DAC reference settling poses a speed bottleneck in chargeredistribution SAR ADCs due to the ringing associated with the parasitic inductances. Although SAR ADCs have been the subject of intense research in recent years, scant attention has been laid on the design of high-performance on-chip reference voltage buffers. The estimation of important design parameters of the buffer as well iv critical specifications such as power-supply sensitivity, output noise, offset, settling time and stability have been elaborated upon in this dissertation. The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages. The 10-bit SAR ADC utilizes split-array capacitive DACs to reduce area and power consumption. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the ...

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Harikumar¹

2016

Linköping Studies in Science and Technology. Dissertations

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“…Even with advanced rectifiers, such as the reconfigurable resonant regulating rectifier (R 3 rectifier), the ripple of the rectified voltage can still be measured in tens of mV [ 1 ]. For conventional SAR ADCs adopted in such systems [ 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 ], a dedicated regulator is needed to stabilize the reference voltage against the ADC core. However, the regulator consumes significant power [ 2 , 3 , 4 ].…”

Section: Introductionmentioning

confidence: 99%

“…For conventional SAR ADCs adopted in such systems [ 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 ], a dedicated regulator is needed to stabilize the reference voltage against the ADC core. However, the regulator consumes significant power [ 2 , 3 , 4 ]. Besides, decoupling capacitors of a few hundred pF or larger values are needed to maintain the stable operation of the regulator [ 10 ].…”

Section: Introductionmentioning

confidence: 99%

A 10-Bit 300 kS/s Reference-Voltage Regulator Free SAR ADC for Wireless-Powered Implantable Medical Devices

Yang

Zhou

Liu

et al. 2018

Sensors

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This paper presents a reference-voltage regulator free successive-approximation-register analog-to-digital converters (SAR ADC) with self-timed pre-charging for wireless-powered implantable medical devices. Assisted by a self-timed pre-charging technique, the proposed SAR ADC eliminates the need for a power-hungry reference-voltage regulator and area-consuming decoupling capacitor while maintaining insensitivity to the supply voltage fluctuation. Fabricated with a 0.18-µm complementary metal–oxide–semiconductor (CMOS) technology, the proposed SAR ADC achieves a Signal To Noise And Distortion Ratio (SNDR) of 53.32 dB operating at 0.8 V with a supply voltage fluctuation of 50 mVpp and consumes a total power of 2.72 µW at a sampling rate of 300 kS/s. Including the self-timed pre-charging circuits, the total figure-of-merit (FOM) is 23.9 fJ/conversion-step and the total area occupied is 0.105 mm2.

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“…The RVBuffer should have rapid settling speed which makes it very power-hungry. The power consumption of the RVBuffer is fifteen times [5] or even twenty-eight times [4] as much as that of the SAR ADC core. The Walden FoM increases dramatically when considering the RVBuffer.…”

Section: Introductionmentioning

confidence: 99%

A 700-MS/s 6-bit SAR ADC with partially active reference voltage buffer

Zhao

Yang

2018

IEICE Electron. Express

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This paper presents a 700-MS/s 6-bit SAR ADC with a novel on-chip reference voltage buffer in a 40-nm CMOS Low-Leakage (LL) process. The reference voltage buffer is partially active depending on the operation state of the SAR ADC. The large driving current is provided only when the Capacitive Digital-to-Analog Converter (CDAC) is settling. This approach achieves 42% power reduction for the reference voltage buffer, which helps to improve the Figure-

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A Programmable 10b up-to-6MS/s SAR-ADC Featuring Constant-FoM with On-Chip Reference Voltage Buffers

Cited by 14 publications

References 3 publications

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

A 10-Bit 300 kS/s Reference-Voltage Regulator Free SAR ADC for Wireless-Powered Implantable Medical Devices

A 700-MS/s 6-bit SAR ADC with partially active reference voltage buffer

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