A Programmable Calibration/BIST Engine for RF and Analog Blocks in SoCs Integrated in a 32 nm CMOS WiFi Transceiver

Carballido, J Martinez; Hermosillo, J.; Veloz, Arturo; Arditti, David; Río, A. del; Borrayo, E.; Guzmán, Martha Elva Ramírez; Lakdawala, Hasnain; Verhelst, Marian

doi:10.1109/jssc.2013.2253401

Cited by 13 publications

(10 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…BACKGROUND Several BIST controllers for analog and digital circuits are proposed in the literature. A representative description of calibration methods for performance improvement can be found in [3] and [4]. Different techniques for trim optimizations are proposed in [5] and [6].…”

Section: Introductionmentioning

confidence: 99%

A novel technique for interdependent trim code optimization

Bongale

Sundaresan²,

Ghosh

et al. 2016

2016 IEEE 34th VLSI Test Symposium (VTS)

View full text Add to dashboard Cite

As integrated circuits become increasingly complex, the fabrication process renders them more marginal to specification parameters. Consequently, these circuits have to be tuned post fabrication to compensate for process marginality and thereby optimize their performance as well as to improve yields. This process of tuning is commonly termed as trimming, wherein the right set of digital trim codes is identified and used as a calibration setting by writing these codes into the hardware configuration registers. This paper addresses the problem of carrying out multi-variable trims involving two or more parameters, codes for which must be simultaneously searched and set, in order to attain the desired performance of the circuit. A novel low-cost hardware implementation of the Simplex minimization algorithm with speed-up improvements is described. This implementation is amenable for on-chip BIST (built-in self-test) and can also be directly implemented as part of the ATE (automatic test equipment) program. Experimental results are presented on two industrial circuits. Improvements in terms of trim code search time and attaining better performance are shown.

show abstract

Section: Introductionmentioning

confidence: 99%

A novel technique for interdependent trim code optimization

Bongale

Sundaresan²,

Ghosh

et al. 2016

2016 IEEE 34th VLSI Test Symposium (VTS)

View full text Add to dashboard Cite

show abstract

“…The dirty radio approach proposes that all undesirable effects in the analog front end could be compensated in the digital front end by means of pure digital signal processing. In the future, it is desirable that RF with tuning capabilities will also have digital signal processing capabilities to compensate any hardware imperfection effects . Specifically, it could be very convenient to use digital signal processing to clean some kind of undesirable distortions .…”

Section: Introductionmentioning

confidence: 99%

Digital compensation of second‐ and third‐order nonlinear distortions generated by blocker signals

Mendoza‐Valencia

Laguna-Sanchez

Prieto‐Guerrero

2016

IEEJ Transactions Elec Engng

View full text Add to dashboard Cite

Deeply integrated systems in chips commonly include a digital and an analog front end on the same die. These analog frontend schemes for wireless communications could be implemented under the concept called software-defined radio (SDR). Digital signal processing is commonly used to perform signal filtering and channel equalization, and, recently, to improve front-end radio performance by removing the undesirable effects of the analog front-end imperfections. These wide-band SDR are currently implemented without the surface acoustic wave (SAW) filter, because it is difficult to integrate a highly configurable one, as is required in wide-band systems. An analog front end without this filter has no efficient protection against blocker signal effects, specifically against nonlinear distortions due to the analog front-end imperfections. This paper proposes an algorithm to simultaneously remove second-and third-order nonlinear distortions caused by a blocker signal, departing from a behavioral model and a band-pass sampling pure digital algorithm to recover the blocker signal information.

show abstract

“…Additionally, the use of detectors in advanced CMOS processes in the context of an RF block that is part of a SoC entails drawbacks and benefits. On one hand, variability is a main issue in deep-submicrometer CMOS processes [16] and its effects on the detectors themselves may lead to errors in the internal measurements [3], [9]. On the other hand, SoCs implemented in advanced CMOS processes include powerful digital processing capabilities for implementing the SoC functions, which can also be applied to simplify and improve the design of RF parts, or aid to put in place BiST/BiSC capabilities [5].…”

Section: Introductionmentioning

confidence: 99%

Digitally Assisted CMOS RF Detectors With Self-Calibration for Variability Compensation

Barabino

Silveira

2015

IEEE Trans. Microwave Theory Techn.

View full text Add to dashboard Cite

In this paper, a technique of digitally assisted RF detectors with variability compensation is proposed. It enables the ability to obtain a high dynamic-range linear-in-dB characteristic with a small footprint. Digital assistance is used to correct for a nonlinear characteristic and to perform a self-calibration. In state-of-the-art CMOS RF systems-on-chip (SoCs), the digital capabilities required for this technique would not represent an overhead for the design, as they are already available. The self-calibration compensates for the process variability relying on internal dc measurements and statistical information derived from the statistical models provided by the foundry. This technique would benefit SoCs, which implement built-in self test or built-in self calibration by enabling multiple high dynamic-range internal RF measurements, while complying with tight area and power budgets. A proof-of-concept detector cell is presented in a 90-nm CMOS process, which provides a maximum linearity error of 1.5 dB and a 33-dB dynamic range at 2 GHz after digital correction. The circuit occupies an area of 0.004 mm and consumes a maximum of 240-A from a 1.2-V supply. The results are confirmed by measurements performed on ten samples. Index Terms-Built-in-self-calibration (BiSC), built-in-self-test (BiST), deep-submicrometer CMOS, digitally assisted, linearin-dB detector, millimeter wave (mmW), RF, system-on-chip (SoC), variability compensation.

show abstract

A Programmable Calibration/BIST Engine for RF and Analog Blocks in SoCs Integrated in a 32 nm CMOS WiFi Transceiver

Cited by 13 publications

References 14 publications

A novel technique for interdependent trim code optimization

A novel technique for interdependent trim code optimization

Digital compensation of second‐ and third‐order nonlinear distortions generated by blocker signals

Digitally Assisted CMOS RF Detectors With Self-Calibration for Variability Compensation

Contact Info

Product

Resources

About