Digitally Assisted CMOS RF Detectors With Self-Calibration for Variability Compensation

Abstract

In this paper, a technique of digitally assisted RF detectors with variability compensation is proposed. It enables the ability to obtain a high dynamic-range linear-in-dB characteristic with a small footprint. Digital assistance is used to correct for a nonlinear characteristic and to perform a self-calibration. In state-of-the-art CMOS RF systems-on-chip (SoCs), the digital capabilities required for this technique would not represent an overhead for the design, as they are already available. The self-calibration compensates for the process variability relying on internal dc measurements and statistical information derived from the statistical models provided by the foundry. This technique would benefit SoCs, which implement built-in self test or built-in self calibration by enabling multiple high dynamic-range internal RF measurements, while complying with tight area and power budgets. A proof-of-concept detector cell is presented in a 90-nm CMOS process, which provides a maximum linearity error of 1.5 dB and a 33-dB dynamic range at 2 GHz after digital correction. The circuit occupies an area of 0.004 mm and consumes a maximum of 240-A from a 1.2-V supply. The results are confirmed by measurements performed on ten samples. Index Terms-Built-in-self-calibration (BiSC), built-in-self-test (BiST), deep-submicrometer CMOS, digitally assisted, linearin-dB detector, millimeter wave (mmW), RF, system-on-chip (SoC), variability compensation.

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