A programmable simulator for analyzing the block data flow architecture

This paper presents an approach to implementing the parallel Kalman filter. The parallel Kalman filter is computationally intensive and hence complex due to the inherent matrix operations. Often, the filter cannot be computed in real time when the system has a large number of state variables. Discussed is a method for achieving almost real-time performance. In addition, a method for determining stability of the Kalman filter is presented. This method involves the use a paradigm that achieves high performance and close to real time results while maintaining accuracy for the Kalman filter. In addition, the paradigm shows an improvement of the processor utilization over other implementations and provides flexibility in terms of the hardware used for implementation.

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An algorithm and architecture for the parallel solution of systems of linear equations

Wilburn

Alexander

Conference Proceedings of the 1996 IEEE Fifteenth Annual International Phoenix Conference on Computers and Communications

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This paper evaluates a paradigm for the efficient utilization of commercially available processors to implement serial algorithms on a parallel architecture. We present an architecture based on this paradigm as well as an algorithm for the parallel solution of a nonhomogeneous system of linear equations with constant coefficients. Major advantages stem from its systolic-like array structure and the versatility of fully programmable processor elements. The method uses a Givens rotation implementation of the well known QR factorization. Unlike other direct methods of factorization followed by backsubstitution, this implementation of the algorithm avoids the backsubstitution bottleneck. The computational complexity of this feedforward direct method of solving nonsingular systems of linear equations is on the order that of QR matrix factorization. Due to the programmability of the processor in the array, the mapping of this algorithm extends to an entire family of algorithms. We map this family of algorithms onto the novel architecture and present a comprehensive performance analysis. Performance results identify the algorithm/architecture combination as a cost effective, efficient method which exhibits speedup that is directly proportional to the number of processors used.

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A programmable simulator for analyzing the block data flow architecture

Cited by 4 publications

References 4 publications

Parallel image processing with the block data parallel architecture

Parallel image processing with the block data parallel architecture

Parallel processing and stability analysis of the Kalman filter

An algorithm and architecture for the parallel solution of systems of linear equations

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