A Programmable Stream Processing Engine for Packet Manipulation in Network Processors

Meitinger, Michael; Ohlendorf, Rainer; Wild, Thomas; Herkersdorf, Andreas

doi:10.1109/isvlsi.2007.16

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B Architecture and Demonstrator1

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2008

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Cited by 7 publications

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“…data replace/insert, IP checksum update). It is programmed by specific assembler like instructions sent along with the packet (see [14]). …”

Section: B Architecture and Demonstratormentioning

confidence: 99%

FlexPath NP - A network processor architecture with flexible processing paths

Meitinger

Ohlendorf

Wild

et al. 2008

2008 International Symposium on System-on-Chip

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In this paper we present a FlexPath Network Processor implementation, a platform with flexible, reconfigurable processing paths for packet processing. The path decision is made in hardware based on a packet's network application. Packets may be processed by a CPU or even completely in hardware. With our demonstrator the performance of different processing paths is shown for a scenario with simple IPv4 forwarding traffic mixed with IPSec packets. We show that flexible path selection significantly improves the system's performance. The specific FlexPath concepts are also applicable to other NP architectures.

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“…data replace/insert, IP checksum update). It is programmed by specific assembler like instructions sent along with the packet (see [14]). …”

Section: B Architecture and Demonstratormentioning

confidence: 99%