A proposed high manufacturability strain technology for high-k/metal gate SiGe-SOI CMOSFET

Yeh, Wen Kuan; Cheng, C. Y.; Yang, Yi-Lin; Lin, Chien‐Ting; Lai, Chih‐Ming; Chen, Y.W.; Hsu, Cheng Hsing; Yang, Cheng; Chen, P. Y.

doi:10.1109/soi.2011.6081699

Cited by 1 publication

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“…To retard the non-uniform channel carrier transport and the Fermi-level pinning effect [9] influencing the threshold voltage (V T ), the metal-gate (MG) [10][11][12] process replacing the poly-gate process was used. Owing to the desired minimization of crystallization of gate dielectric harmful to gate leakage and related dielectric constant (kvalue), the gate-last [13][14][15] (GL) process was manipulated in this time. In addition, the adequately deposited impurity or stacked layer in Hf-based gate dielectric is a promising method to reduce the possibility of poly-or nanocrystallization of gate dielectric around 700 o C, which means that the crystallization temperature can be raised up more.…”

Section: Process Flowmentioning

confidence: 99%

CLM effect for 28nm stacked HK nmosfets after DPN treatment with different annealing temperatures

Wang

Lee

et al. 2014

2014 International Symposium on Next-Generation Electronics (ISNE)

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In this work, it can be seen that the effect of channel length modulation for NMOSFETs under high-k/metal gate deposition depicts a minor deviation with different nitridation annealing temperatures. This consequence, however, strongly correlates to the channel length and the gate voltage playing as a vertical field. As the channel length is narrowed down, the horizontal field coming from drain voltage on the channel is increased more and compresses the effective channel length, reflecting on the Early voltage V A . In the past, all of I D vs. V D curves after extrapolation would approach an identical intersection point. But this phenomenon should be modified more right now.

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