A proposed reliable and power efficient 14T full adder circuit design

Subramaniam, S.; Wilson, Tan Wee Xin; Singh, Ajay Kumar; Murthy, G. Ramana

doi:10.1109/tencon.2017.8227834

Cited by 4 publications

(2 citation statements)

References 10 publications

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“…Similarly, 6T MUX design and 3T ANI-XOR circuit are the smallest CMOS logic gates in their class that deliver correct function without inverted inputs. Although 3T and 4T CMOS XOR gates are reported in the literature [26], [27], they rely on nMOS or pMOS only pass gates that does not pass logic 0 or logic 1 states equally well. Unlike these previous examples or conventional CMOS pass gates that demand twice the area or almost an order of magnitude larger power dissipation, the proposed WFE-optimized 4T and 3T XOR gates utilize full CMOS blocks that can pass logic 0/1 levels either equally well or better than single-gate counterparts owing to dual-gate action of the FinFET.…”

Section: Discussionmentioning

confidence: 99%

Ultracompact and Low-Power Logic Circuits via Workfunction Engineering

Canan

Kaya

Kodi

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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An extensive analysis of sub-10-nm logic building blocks utilizing ultracompact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided. WFE sets the WF in the contacts as well as two independent gates of an ambipolar Schottky-barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor. Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to ×10) dissipation can be implemented. To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks, including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop, and 4T AND-OR-invert (AOI) gates, are developed. Besides the logic verification using 7-nm devices, the dynamic performance of the proposed logic circuits is also analyzed. The comparative simulation study shows that WFE in independent-gate SB-FinFETs can lead to absolutely minimalist CMOS logic blocks without significant degradation to overall power-delay product (PDP) performance. INDEX TERMS 3T-XOR, 4T AND-OR-invert (AOI), 6T 4-to-1 multiplexer (MUX), ambipolar, CMOS logic gates, nanotechnology, Schottky-barrier MOSFET, tunneling.

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Section: Discussionmentioning

confidence: 99%

Ultracompact and Low-Power Logic Circuits via Workfunction Engineering

Canan

Kaya

Kodi

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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“…Fewer transistors with more connections might cause large wire loads and unexpected delays. Moreover, PTL-based cells might suffer from issues such as threshold loss [22,23], weak driving capacity [24], and uneven delay and power distribution. Circuits with PTL need to be properly designed to fully exploit their advantages.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier

Yin

Pan

et al. 2023

Electronics

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With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and multiplier circuits due to the low count of transistors and low-power characteristics. In this paper, we present a novel full adder based on pass transistors. The proposed full adder consists of 18 transistors. The post-layout simulation shows a 13.78% of power reduction compared to conventional CMOS full adders. Moreover, we propose an 8-bit signed multiplier based on the proposed full adder. The post-layout simulation shows an 8% power reduction compared to the multiplier produced by the Design Compiler synthesis tool. Compared to the existing work with a similar process, our work achieved only 19.02% of the power-delay product and 3.5% of the area-power product.

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