Ultracompact and Low-Power Logic Circuits via Workfunction Engineering

Canan, Talha Furkan; Kaya, Savaş; Kodi, Avinash; Louri, Ahmed

doi:10.1109/jxcdc.2019.2962494

Cited by 9 publications

(5 citation statements)

References 25 publications

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“…To gain more insight into the practical implications of our proposal, we compare the AFA with the state-of-the-art accurate SW [36], 7nm CMOS [37], SHE [38], DWM [39], accurate and approximate 45nm CMOS [40], MTJ [41], and Spin-CMOS [33] counterparts in terms of energy, delay, and area (the number of utilized devices). We base our evaluation on the following assumptions: (i) Magnetoelectric (ME) cells are utilized for SW excitation and detection.…”

Section: Performance Evaluationmentioning

confidence: 99%

“…Table 4 presents the results of the evaluation and comparison. Inspecting the Table, it is clear that AFA outperforms state-of-the-art 7nm CMOS [37] accurate FA by an energy reduction of approximately 6%, while exhibiting a more than 2 orders of magnitude larger delay. Furthermore, AFA saves approximately 56% and 20% energy while requiring 15x and 18x larger delay when compared with 45nm CMOS based accurate and approximate FAs, respectively, while having the same error rate as the approximate FA in [40].…”

Section: Performance Evaluationmentioning

confidence: 99%

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Spin Wave Based Approximate Computing

Mahmoud

Vanderveken

Ciubotaru

et al. 2022

IEEE Trans. Emerg. Topics Comput.

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By their very nature Spin Waves (SWs) enable the realization of energy efficient circuits, as they propagate and interfere within waveguides without consuming noticeable energy. However, SW computing can be even more energy efficient by taking advantage of the approximate computing paradigm as many applications, e.g., multimedia and social media, are error-tolerant. In this paper, we propose an ultra-low energy Approximate Full Adder (AFA) and an Approximate 2-bit inputs Multiplier (AMUL). AFA consists of one Majority gate whereas AMUL is built by means of 3 AND gates. We validate the correct functionality of our proposal by means of micromagnetic simulations and evaluate AFA's figures of merit against state-of-the-art accurate SW, 7nm CMOS, Spin Hall Effect (SHE), Domain Wall Motion (DWM), accurate and approximate 45nm CMOS, Magnetic Tunnel Junction (MTJ), and Spin-CMOS FA implementations. Our results indicate that AFA consumes 38% and 6% less energy than state-of-the-art accurate SW and 7nm CMOS FA implementations, respectively. Moreover, it saves 56% and 20% energy when compared with accurate and approximate 45nm CMOS counterparts, respectively. Furthermore, it provides 2 orders of magnitude energy reduction when compared with accurate SHE, accurate and approximate DWM, MTJ, and Spin-CMOS, counterparts. In addition, it achieves the same error rate as approximate 45nm CMOS and Spin-CMOS FAs whereas it exhibits 50% less error rate than the approximate DWM FA. Last but not least, it outperforms its contenders in terms of area by saving at least 29% chip real-estate. AMUL is evaluated and compared with state-of-the-art SW and 16nm CMOS accurate and approximate designs. The evaluation results indicate that AMUL energy consumption is at least 2.8x and 2.6x smaller than the one of state-of-the-art SW and 16nm CMOS accurate and approximate designs, respectively. AMUL has an error rate of 25%, whereas the approximate CMOS multiplier has an error rate of 38%, and requires at least 64% less chip real-estate than the CMOS counterpart.

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Section: Performance Evaluationmentioning

confidence: 99%

Section: Performance Evaluationmentioning

confidence: 99%

Spin Wave Based Approximate Computing

Mahmoud

Vanderveken

Ciubotaru

et al. 2022

IEEE Trans. Emerg. Topics Comput.

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“…Other work focused on the design of the highspeed multiplexer based on a decomposition algorithm [32]. Ultra-compact architectures for various combinational circuits, including decoders and multiplexers, as described in [33], use simple transmission gate logic. Therefore, adding digital decoder and multiplexer attributes to a single cell is beneficial for some SoC applications.…”

Section: Finfet Device and Technologymentioning

confidence: 99%

A 16 nm FinFET circuit with triple function as digital multiplexer, active-high and active-low output decoder for high-performance SRAM architecture

Battini¹,

Sivani²

2022

Semicond. Sci. Technol.

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This paper presents a FinFET based Single Circuit (FSC) used to realize Active-High output Decoder (AHD), Active-Low output Decoder (ALD), and Digital Multiplexer. The input signal is traversed through a single transmission gate irrespective of the size of FSC is the uniqueness of the proposed multiplexer. The new architectures of FSC use an equal number of n-FinFET and p-FinFET devices, requiring few transistors compared to CMOS designs. Three novel circuits are created using various logic styles following the same architecture. The FSC is compared with the similar circuits, and on average, the results of power dissipation and delay in the worst case show that FSC is better by 14\%, and 18\%, respectively. An FSC is created and extensively simulated at 16nm FinFET technology using Eldo software. All the circuits are designed for 0.75V, 1V, and 1.25V and are stimulated with multiple input frequencies. The proposed circuit is best suitable for row address decoders and column multiplexers of SRAM.

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“…The proposed FA is assessed and compared with the state-of-the-art CMOS 30 , Magnetic Tunnel Junction MTJ 31,32 , Spin Hall Effect SHE 33 , Domain Wall Motion DWM 34 , and Spin-CMOS 35 based FA in terms of energy, delay, and area (the number of utilized devices). In the evaluation and comparison, the following assumptions are made: propagation delay in the waveguide, which is extracted from micromagnetic simulation and it is 1.18 ns.…”

Section: A Performance Evaluationmentioning

confidence: 99%

Spin Wave Based Full Adder

Mahmoud¹,

Vanderveken²,

Ciubotaru³

et al. 2021

Preprint

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Spin Waves (SWs) propagate through magnetic waveguides and interfere with each other without consuming noticeable energy, which opens the road to new ultra-low energy circuit designs. In this paper we build upon SW features and propose a novel energy efficient Full Adder (FA) design consisting of The FA 1 Majority and 2 XOR gates, which outputs Sum and Carry-out are generated by means of threshold and phase detection, respectively. We validate our proposal by means of MuMax3 micromagnetic simulations and we evaluate and compare its performance with state-of-the-art SW, 22nm CMOS, Magnetic Tunnel Junction (MTJ), Spin Hall Effect (SHE), Domain Wall Motion (DWM), and Spin-CMOS implementations. Our evaluation indicates that the proposed SW FA consumes 22.5% and 43% less energy than the direct SW gate based and 22nm CMOS counterparts, respectively. Moreover it exhibits a more than 3 orders of magnitude smaller energy consumption when compared with state-of-the-art MTJ, SHE, DWM, and Spin-CMOS based FAs, and outperforms its contenders in terms of area by requiring at least 22% less chip real-estate.

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Ultracompact and Low-Power Logic Circuits via Workfunction Engineering

Cited by 9 publications

References 25 publications

Spin Wave Based Approximate Computing

Spin Wave Based Approximate Computing

A 16 nm FinFET circuit with triple function as digital multiplexer, active-high and active-low output decoder for high-performance SRAM architecture

Spin Wave Based Full Adder

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