A Prototype Multithreaded Associative SIMD Processor

Schaffer, Kevin; Walker, Robert A.

doi:10.1109/ipdps.2007.370471

Cited by 5 publications

(5 citation statements)

References 9 publications

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“…Comparisons between the power of these models and other well-known computational models are given in [45,64,65]. A possible implementation of a multi-threaded associative processor is also investigated in [52].…”

Section: Observations and Consequences Of The Preceding Resultsmentioning

confidence: 99%

“…So the transfer of data speed is not a bottleneck for building an associative processor to accommodate realistic size ATC problems. See references [39,48,49,47,50,51,27,52,53] to find more information about how to implement AP hardware. Another issue involving AP properties is how the constant time operations can be supported in AP and how can we be sure they actually run in constant time.…”

Section: Ap Propertiesmentioning

confidence: 99%

“…The key to AP hardware design is [53,54,55,52]: 1) high memory-to-PE bandwidth, and 2) low level synchronous operation supported by the i) elimination of branches in low level loops, and ii) the elimination of low level barrier synchronism. In the STARAN and the ASPRO, these abilities were supported by corner turning the data and assigning one record per processor, the multi-dimensional array memory (and flip network) and mask register hardware.…”

Section: Ap Propertiesmentioning

confidence: 99%

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Comparisons of air traffic control implementations on an associative processor with a MIMD and consequences for parallel computing

Yuan¹,

Baker²,

Meilander³

2013

Journal of Parallel and Distributed Computing

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This paper has two complementary focuses. The first is the system design and algorithmic development for air traffic control (ATC) using an associative SIMD processor (AP). The second is the comparison of this implementation with a multiprocessor implementation and the implications of these comparisons. This paper demonstrates how one application, ATC, can more easily, more simply, and more efficiently be implemented on an AP than is generally possible on other types of traditional hardware. The AP implementation of ATC will take advantage of its deterministic hardware to use static scheduling. The software will be dramatically smaller and cheaper to create and maintain. Likewise, a large AP system will be considerably simpler and cheaper than the MIMD hardware currently used. While APs were used for ATC-type applications earlier, these are no longer available. We use a ClearSpeed CSX600 accelerator to emulate the AP solutions of ATC on an ATC prototype consisting of eight data-intensive ATC real-time tasks. Its performance is compared with an 8-core multiprocessor (MP) using OpenMP. Our extensive experiments show that the AP implementation meets all deadlines while the MP will regularly miss a large number of deadlines. The AP code will be similar in size to sequential code for the same tasks and will avoid all of the additional support software needed with an MP to handle dynamic scheduling, load balancing, shared resource management, race conditions, * Corresponding author Email addresses: myuan@cs.kent.edu (Man(Mike) Yuan), jbaker@cs.kent.edu (Johnnie W. Baker), wllcm@att.net (Will C. Meilander) 1 This is the first author footnote. Preprint submitted to Journal of Parallel and Distributed Computing August 15, 2012false sharing, etc. At this point, essentially only MIMD systems are built. Many of the advantages of using an AP to solve an ATC problem would carry over to other applications. AP solutions for a wide variety of applications will be cited in this paper. Applications that involve a high degree of data parallelism such as database management, text processing, image processing, graph processing, bioinformatics, weather modeling, managing UAS (Unmanned Aircraft Systems or drones) etc, are good candidates for AP solutions. This raises the issue of whether we should routinely consider using non-multiprocessor hardware like the AP for applications where substantially simpler software solutions will normally exist. It also raises the question of whether the use of both AP and MIMD hardware in the same system could provide more versatility and efficiency. Either the AP or MIMD could serve as the primary system but could hand off jobs it could not handle efficiently to the other system.

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Section: Observations and Consequences Of The Preceding Resultsmentioning

confidence: 99%

Section: Ap Propertiesmentioning

confidence: 99%

Section: Ap Propertiesmentioning

confidence: 99%

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Comparisons of air traffic control implementations on an associative processor with a MIMD and consequences for parallel computing

Yuan¹,

Baker²,

Meilander³

2013

Journal of Parallel and Distributed Computing

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“…To further improve performance, a fully pipelined broadcast network was combined with hardware multithreading. The multithread associative SIMD processor (MTASC) [11] prototyped in 2007, with 16 PEs with 1KB of memory per PE, 16 hardware thread contexts, operates at clock speed of 75Mhz. The control unit in this model is a multithreaded scalar processor.…”

Section: Related Workmentioning

confidence: 99%

Broadcast with mask on a massively parallel processing on a chip

Krichene

Baklouti

Abid

et al. 2012

2012 International Conference on High Performance Computing &Amp; Simulation (HPCS)

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The delay of instructions broadcast has a significant impact on the performance of Single Instruction Multiple Data (SIMD) architecture. This is especially true for massively parallel processing Systems-on-Chip (mppSoC), where the processing stage and that of setting up the communication mechanism need several clock periods. Subnetting is the strategy used to partition a single physical network into more than one smaller logical sub-networks (subnets). This technique better controls the broadcast instructions domain and the data traffic between network nodes. Furthermore, it allows to separate synchronous communications from asynchronous processing which maintains reliable communications and rapid processing through parallel processors. This paper describes the design of a communication model called broadcast with mask. This model is dedicated to mppSoC architecture with a huge number of processor elements because it maintains performances even when the number of processors increases. Simulation results and an FPGA implementation validate our approach.

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“…Although a hardware prototype multithreaded associative SIMD (an alternative version of ASC) had been developed using FPGA by Schaffer [12] in 2007, no hardware prototype of the MASC model has been developed yet. This is the first time that the MASC model has been completely implemented on a platform true to the original MASC description.…”

Section: Introductionmentioning

confidence: 99%

A Software Implementation of a Cycle Precision Simulator of a Multiple Associative Model

Chantamas

Baker

2010

Informatics

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The Multiple Associative Computing (MASC) parallel model is a generalization model of an Associative Computing (ASC) parallel model designed to support multiple ASC data parallel threads by using control parallelism. The MASC model is designed to combine the advantages of both Single Instruction Stream Multiple Data Streams (SIMD) and Multiple Instruction Streams Multiple Data Streams (MIMD) models. Here is the first time that a complete description of MASC model has been implemented (in software) true to its original description. A cycle precision simulator is built to demonstrate the performance of MASC on various multithreaded algorithms. The simulator is a software prototype for the model with sufficient software details to allow it to be converted into a hardware prototype of the model. If a reasonable limit for the number of threads simultaneously supported is assumed, the resulting hardware design is not only easily to implement, but can easily support a huge number of processing units and is a excellent candidate architecture for supporting large scale (e.g., terascale and petascale) computing. Experimental results shows that, when processing large-scale instances using multiple workers, the algorithm executed by the MASC model using a static task assignment scheme provides strong scaling with constant time overhead.

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A Prototype Multithreaded Associative SIMD Processor

Cited by 5 publications

References 9 publications

Comparisons of air traffic control implementations on an associative processor with a MIMD and consequences for parallel computing

Comparisons of air traffic control implementations on an associative processor with a MIMD and consequences for parallel computing

Broadcast with mask on a massively parallel processing on a chip

A Software Implementation of a Cycle Precision Simulator of a Multiple Associative Model

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