A Pseudo-Pseudo-Differential ADC Achieving 105dB SNDR in 10kHz Bandwidth Using Ring Amplifier Based Integrators

Lee, Calvin Yoji; Venkatachala, Praveen Kumar; ElShater, Ahmed; Moon, Un-Ku

doi:10.1109/tcsii.2021.3060011

Cited by 4 publications

(3 citation statements)

References 16 publications

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“…It dissipates 516 μW under a 1.5 V supply. (1) Schematic simulation results; (2) Post layout simulation results; Others are from measurements; (3) FoM S = SNDR Peak + 10 log(BW/power).…”

Section: Discussionmentioning

confidence: 99%

“…The ΣΔ ADC consists of an analog modulator and a digital filter, while analog modulator is the core circuit of the Sigma-Delta ADC. Among them, the continuous-time (CT) Sigma-Delta modulator (DSM) does not require high build-up speed of the integrator, which is beneficial for low-power design [3]. However, its signal path characteristics (e.g., noise shaping function) are closely related to the process-voltage-temperature (PVT) variation, the modulator has more stringent component matching requirements, and the SNDR is sensitive to clock jitter [4,5].…”

Section: Introductionmentioning

confidence: 99%

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A 516 μW, 121.2 dB-SNDR, and 125.1 dB-DR Discrete-Time Sigma-Delta Modulator with a 20 kHz BW

Kong

2022

Journal of Sensors

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This article proposed a discrete-time single-loop 3rd order 5-bit Sigma-Delta (ΣΔ) modulator for the audio applications. In this modulator, a feed forward path is used to relax the design requirement of amplifier, which can reduce integrator’s output swing. And a 5-bit asynchronous SAR ADC combined with analog summing is adopted to quantify the summation of feedforward signal and loop filter output, which can significantly reduce power consumption. In addition, chopper stabilization technique is used to alleviate the flicker noise introduced by the first integrator. To eliminate the nonlinearity introduced by multibit quantizer, an improved data weighted average algorithm calibration circuit is proposed. The proposed modulator is implemented in 130 nm technology with a 1.12 mm2 core area. Operating at a 2.56MS/s sampling rate, post layout simulation results show that the modulator realizes 121.2-dB SNDR and 125.1-dB DR in a 20 kHz signal bandwidth, it dissipating 516 μW from 1.5 V supply. It also achieves the energy efficiency, as demonstrated by a Schreier figure of merit (FoMS) of 197 dB.

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“…It dissipates 516 μW under a 1.5 V supply. (1) Schematic simulation results; (2) Post layout simulation results; Others are from measurements; (3) FoM S = SNDR Peak + 10 log(BW/power).…”

Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 516 μW, 121.2 dB-SNDR, and 125.1 dB-DR Discrete-Time Sigma-Delta Modulator with a 20 kHz BW

Kong

2022

Journal of Sensors

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“…The steady-state bandwidth is also kept low to filter the noise in the first stage, which provides additional area and power savings. The DT ADC with PPD-based ring amplifier [118] achieves an FoM S of 185.3 dB with an area of 0.0375 mm 2 .…”

Section: ) Active Integratorsmentioning

confidence: 99%

Design Techniques for Energy-Efficient Analog-to-Digital Converters

Jang,

Tang,

Lim

et al. 2023

IEEE Open J. Solid-State Circuits Soc.

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The energy efficiency of analog-to-digital converters (ADCs) has improved steadily over the past 40 years, with the best reported ADC efficiency improving by nearly six orders of magnitude over the same period. The best figure-of-merit (FoM) is achieved with a limited class of ADC in terms of resolution and speed, but the coverage of the best FoM ADC has been expended. Many ADCs with the record FoM open up new applications and often incorporate multiple combinations of architectural and circuit innovations. It would be very interesting to follow a path of relentless optimization that could be useful to further expand the operating bandwidth of energy-efficient ADCs. To help along this path, this review article discusses the design techniques that focus on optimizing energy efficiency, involving successive approximation, pipelining, noise-shaping, and continuous-time operation.INDEX TERMS Analog-to-digital converter (ADC), continuous-time (CT), delta-sigma modulation, energy efficient, low power, noise-shaping (NS), pipelining, successive approximation.

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A 16- Bit 100kHz Bandwidth Pseudo-Pseudo-Differential Delta-Sigma ADC

Lee

Wang

et al. 2023

2023 IEEE International Symposium on Circuits and Systems (ISCAS)

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A Pseudo-Pseudo-Differential ADC Achieving 105dB SNDR in 10kHz Bandwidth Using Ring Amplifier Based Integrators

Cited by 4 publications

References 16 publications

A 516 μW, 121.2 dB-SNDR, and 125.1 dB-DR Discrete-Time Sigma-Delta Modulator with a 20 kHz BW

A 516 μW, 121.2 dB-SNDR, and 125.1 dB-DR Discrete-Time Sigma-Delta Modulator with a 20 kHz BW

Design Techniques for Energy-Efficient Analog-to-Digital Converters

A 16- Bit 100kHz Bandwidth Pseudo-Pseudo-Differential Delta-Sigma ADC

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