This paper reports a 12-bit 100-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for low-power wireless and imaging systems. A split-capacitor digitalto-analog converter (CDAC) structure is adopted for reducing the core area and improving the sampling speed. The linearity of the CDAC is calibrated by programming the least-significant-bits (LSBs) capacitor. The unit capacitor in the CDAC array is customized for higher symmetry and reducing their mismatch. Our SAR ADC is based on asynchronous logic, and its timing is controlled by a delaying block in the critical path. The prototype is fabricated in a 65-nm CMOS process with a 1.2 V supply and occupies an active area of 0.029 mm 2 . With a 100-MS/s sampling rate, the measured ENOB scores 10.17 bits for 1.5-MHz input with a figure-of-merit (FoM) of 6.94 fJ/conversion-step. It can achieve 8.83 bits for the Nyquist input signal.INDEX TERMS Successive approximation register (SAR) analog-to-digital converter (ADC), CMOS, split-CDAC, customized unit capacitor, asynchronous logic, figure-of-merit (FoM).

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