No abstract

No abstract

This paper reports a 12-bit 100-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for low-power wireless and imaging systems. A split-capacitor digitalto-analog converter (CDAC) structure is adopted for reducing the core area and improving the sampling speed. The linearity of the CDAC is calibrated by programming the least-significant-bits (LSBs) capacitor. The unit capacitor in the CDAC array is customized for higher symmetry and reducing their mismatch. Our SAR ADC is based on asynchronous logic, and its timing is controlled by a delaying block in the critical path. The prototype is fabricated in a 65-nm CMOS process with a 1.2 V supply and occupies an active area of 0.029 mm 2 . With a 100-MS/s sampling rate, the measured ENOB scores 10.17 bits for 1.5-MHz input with a figure-of-merit (FoM) of 6.94 fJ/conversion-step. It can achieve 8.83 bits for the Nyquist input signal.INDEX TERMS Successive approximation register (SAR) analog-to-digital converter (ADC), CMOS, split-CDAC, customized unit capacitor, asynchronous logic, figure-of-merit (FoM).

This article describes an asynchronous split-CDAC-based SAR ADC with integrated input PGA and an RV-Buffer. The split CDAC structure not only reduces the area of the ADC, but also relieves the driving pressure of the input PGA and RV-Buffer. Using the input PGA instead of the traditional input buffer as the driving circuit of the ADC increases the dynamic input range of the ADC. The proposed on-chip RV-Buffer can provide 1.1 V positive and 0.1 V negative voltage, avoiding the disturbance caused by off-chip reference. This prototype is implemented in a 65 nm CMOS process and occupies an active area of 0.088 mm2. The input PGA can provide 0–18 dB programmable gain with a step of 3 dB. Measurement results show that as the provided gain changes, the ADC’s SNR is best, reaching 50.9 dB, and the SFDR is beat, reaching 62.35 dB at 50 MS/s.