A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer

Abstract

This article describes an asynchronous split-CDAC-based SAR ADC with integrated input PGA and an RV-Buffer. The split CDAC structure not only reduces the area of the ADC, but also relieves the driving pressure of the input PGA and RV-Buffer. Using the input PGA instead of the traditional input buffer as the driving circuit of the ADC increases the dynamic input range of the ADC. The proposed on-chip RV-Buffer can provide 1.1 V positive and 0.1 V negative voltage, avoiding the disturbance caused by off-chip reference. This prototype is implemented in a 65 nm CMOS process and occupies an active area of 0.088 mm2. The input PGA can provide 0–18 dB programmable gain with a step of 3 dB. Measurement results show that as the provided gain changes, the ADC’s SNR is best, reaching 50.9 dB, and the SFDR is beat, reaching 62.35 dB at 50 MS/s.

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

“…At present, precision TDCs implemented on a field programmable gate array (FPGA), with a resolution of fewer than 10 ps, are employed to acquire the time of arrival [ 9 , 10 , 11 ], whereas ADCs [ 12 , 13 , 14 , 15 , 16 ] in application-specific integrated circuits (ASICs) are used for energy measurements and are connected at PCB level to the FPGA, which performs the energy integration algorithm. Owing to a large number of SiPM detector channels, many external ADC chips are required, resulting in relevant system cost and power consumption, which seriously limit the system integration.…”

Linearity Enhancement Techniques for PGA Design

“…There comes another problem when the PGA is driving a large sampling capacitance in some particular applications [ 16 , 17 ], as shown in Figure 3 .…”

“…For example, the THD performance in reference [ 11 ] is only about −50 dB and is not suitable for some applications requiring high linearity. Traditional resistive feedback PGAs are still widely employed in the cases [ 8 , 9 , 16 , 17 ]. However, the linearity of the traditional closed-loop resistive feedback PGAs is limited by the nonidealities of the MOS switches utilized in the feedback resistor array network.…”

Low Voltage Switched-Capacitive-Based Reconfigurable Charge Pumps for Energy Harvesting Systems: An Overview

“…A comparator is a widely used component in the RCP and is essential in the CP control circuitry for circuit-level decisionmaking. One of the common use of the comparator in RCP is to act as a sensing circuit or analog-to-digital converter (ADC) [55][56][57][58][59]. By periodically comparing the varying voltage signal either from the CP input or output path with a predetermined fixed voltage reference [14,15,60], the comparator generates a two-state logic output voltage as shown in Figure 9 which will then feed into the corresponding decision-making control circuits, such as the CR controller.…”