A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS

Li, Manxin; Yao, Yuting; Hu, Biao; Wei, Jipeng; Chen, Yong; Ma, Shunli; Ye, Fan; Ren, Junyan

doi:10.1109/access.2021.3079406

Cited by 15 publications

(9 citation statements)

References 28 publications

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“…At present, precision TDCs implemented on a field programmable gate array (FPGA), with a resolution of fewer than 10 ps, are employed to acquire the time of arrival [ 9 , 10 , 11 ], whereas ADCs [ 12 , 13 , 14 , 15 , 16 ] in application-specific integrated circuits (ASICs) are used for energy measurements and are connected at PCB level to the FPGA, which performs the energy integration algorithm. Owing to a large number of SiPM detector channels, many external ADC chips are required, resulting in relevant system cost and power consumption, which seriously limit the system integration.…”

Section: Introductionmentioning

confidence: 99%

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

Zhang

Zhao

Chen

et al. 2022

Sensors

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A slope analog-to-digital converter (ADC) amenable to be fully implemented on a digital field programmable gate array (FPGA) without requiring any external active or passive components is proposed in this paper. The amplitude information, encoded in the transition times of a standard LVDS differential input—driven by the analog input and by the reference slope generated by an FPGA output buffer—is retrieved by an FPGA time-to-digital converter. Along with the ADC, a new online calibration algorithm is developed to mitigate the influence of process, voltage, and temperature variations on its performance. Measurements on an ADC prototype reveal an analog input range from 0.3 V to 1.5 V, a least significant bit (LSB) of 2.6 mV, and an effective number of bits (ENOB) of 7.4-bit at 600 MS/s. The differential nonlinearity (DNL) is in the range between −0.78 and 0.70 LSB, and the integral nonlinearity (INL) is in the range from −0.72 to 0.78 LSB.

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Section: Introductionmentioning

confidence: 99%

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

Zhang

Zhao

Chen

et al. 2022

Sensors

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“…The proposed hybrid redundancy could provide a certain range of redundancy to tolerate the DAC settling error in this cycle. There was no redundancy in the 6th to 8th cycles in the higher DAC in [32]. There was a certain range of redundancy for each cycle in the higher DAC in the proposed hybrid redundancy method.…”

Section: The Proposed Hybrid Redundancy Methodsmentioning

confidence: 96%

“…There was a certain range of redundancy for each cycle in the higher DAC in the proposed hybrid redundancy method. Moreover, the redundant range of each cycle in the proposed hybrid was lager than the redundant range in [32]. Therefore, the proposed hybrid redundancy was suitable for the bridge structure and the high-resolution ADC.…”

Section: The Proposed Hybrid Redundancy Methodsmentioning

confidence: 97%

“…Table 1 shows the comparison of redundant ranges with different redundant methods. In the 8th cycle (the last cycle of the higher DAC), the redundant range was 0 LSB in [32]. In the 10th cycle (the last cycle of the higher DAC), the redundant range was 20 LSBs.…”

Section: The Proposed Hybrid Redundancy Methodsmentioning

confidence: 99%

“…However, introduced capacitors will reduce the quantization range. The capacitors in an MSB array and LSB array of a bridge DAC capacitor array are split respectively [31,32] and the redundancy can be introduced. However, there is no redundancy for the MSB capacitor in an LSB array, which still produces the settling error.…”

Section: Introductionmentioning

confidence: 99%

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A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

Zheng

Ren

2022

Electronics

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This paper presents a 12-bit, 100 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on a bridge capacitor array with redundancy and non-linearity calibration. The differential non-linearity calibration method was proposed to compensate for the linearity, which is degraded by the parasitic capacitance of the bridge capacitor. To reduce the power dissipation and alleviate the settling error of the DAC capacitor array, a hybrid redundant scheme was proposed. A low-power, high-performance SAR ADC was implemented based on the proposed techniques. This SAR ADC prototype was implemented in 28 nm CMOS technology. Measurement results showed that the proposed SAR ADC could achieve a (signal-to-noise distortion ratio) SNDR of 61.46 dB and 58.82 dB at low and Nyquist input frequencies, respectively, resulting in figure of merits (FOMs) of 8.69 fJ/conversion and 11.8 fJ/conversion step, respectively. The SAR ADC core occupied an active area 0.0227 mm2.

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A 90‐ to 115‐GHz superheterodyne receiver front‐end for W‐band imaging system in 28‐nm complementary metal‐oxide‐semiconductor

Wei

Zhang

et al. 2022

Circuit Theory & Apps

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In this paper, a broadband superheterodyne receiver (RX) front-end for millimeter-wave (mm-Wave) imaging radar is presented. Realized in 28-nm CMOS technology, the proposed RX incorporates a wideband low-noise amplifier (LNA), double-balanced passive mixers for the dual down-conversion, a differential power divider, a differential intermediate frequency filters, a current-mode-logic divider-by-2, and a local oscillator buffers. Wideband technique and layout optimization are taken into consideration in the RX. A fourstage LNA is devised to realize the high gain and low noise figure (NF) with a common-gate input stage and three pseudodifferential common-source stages.Optimized transistor layout and capacitor neutralization technique are developed to improve gain and noise performance. Transformer-based matching networks with the peak-staggered technique are adopted in the LNA to achieve a flatter gain response with a wider bandwidth (BW). The passive double-balanced mixers are implemented with a highly symmetrical layout for broadband down-conversion. Simulation results show that the mm-Wave RX front-end exhibits a BW ranging from 90 to 115 GHz. The simulated NF of our RX is 4.7 dB at 86 GHz. With a supply voltage of 1 V, the presented RX consumes 88.2-mW power and occupies a chip size of 1.6 Â 0.5 mm 2 including all the testing pads. The proposed RX is suitable for W-band imaging systems.

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A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS

Cited by 15 publications

References 28 publications

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

A 90‐ to 115‐GHz superheterodyne receiver front‐end for W‐band imaging system in 28‐nm complementary metal‐oxide‐semiconductor

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