A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

Abstract

This paper presents a 12-bit, 100 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on a bridge capacitor array with redundancy and non-linearity calibration. The differential non-linearity calibration method was proposed to compensate for the linearity, which is degraded by the parasitic capacitance of the bridge capacitor. To reduce the power dissipation and alleviate the settling error of the DAC capacitor array, a hybrid redundant scheme was proposed. A low-power, high-performance SAR ADC was implemented based on the proposed techniques. This SAR ADC prototype was implemented in 28 nm CMOS technology. Measurement results showed that the proposed SAR ADC could achieve a (signal-to-noise distortion ratio) SNDR of 61.46 dB and 58.82 dB at low and Nyquist input frequencies, respectively, resulting in figure of merits (FOMs) of 8.69 fJ/conversion and 11.8 fJ/conversion step, respectively. The SAR ADC core occupied an active area 0.0227 mm2.

A High ENOB 14-Bit ADC without Calibration

“…Another approach to eliminate CDAC nonlinearities is the use of calibration schemes [8][9][10][11][12][13][14][15][16]. The main drawbacks in calibrating CDAC are the barely higher circuit complexity and most important, the testing cost and time [10].…”

A dither‐less bit weight digital background calibration for bridge capacitor digital‐to‐analog converter successive approximation register analog‐to‐digital converters

“…To address these challenges, various calibration methods have been proposed for split‐CDAC SAR ADCs. For example, foreground calibration techniques such as finding optimal digital bit weights [3], correct dummy capacitance value [4], or digital correction codes [5] have been presented. However, foreground calibrations suffer from a drawback that the ADC needs to stop working while being calibrated.…”

“…Achieving signal-tonoise-and-distortion ratio (SNDR) beyond 60 dB, however, typically requires a high-precision capacitor digital-to-analog converter (CDAC) that occupies large silicon area. One approach is to utilize a split CDAC topology [3][4][5][6] where a bridge capacitor attenuates effective capacitance seen from the comparator, thereby aiming to achieve both high resolution and area efficiency. The challenge here is that it is impractical to achieve the desired accuracy for the bridge capacitor due to the process uncertainty.…”

“…However, foreground calibrations suffer from a drawback that the ADC needs to stop working while being calibrated. The background analog calibration methods presented in [4] adjust extra dummy capacitance to linearize the CDAC in analog domain. The challenge here is that designing analog correction circuitries such as a programmable linear capacitor with fine resolutions incurs substantial analog design complexity.…”

“…In this Letter, we present a new digital background calibration method to correct linearity errors arising from both the bridge capacitor inaccuracy and the unit capacitor mismatches. Unlike [4] and [5], our method neither requires extra analog correction circuits nor injects analog dither signal. Compared to [6], our method converges faster because the metastability window in [6] tends to be much narrower than the offset window used in this work.…”