This paper presents a 9-bit pipelined successive-approximation-register (SAR) ADC consisting of 4-stage sub-SAR ADCs using replica-biased dynamic residue amplifiers. The replica-biased amplifier in the 1st stage keeps the output common mode constant over various input voltage conditions, which enables cascading multiple dynamic-amplifier-based pipeline stages. The replica-biased amplifiers from the 2nd to the last stage maintain the differential gain, eliminating the need for bit-weight calibrations. The 1st~3rd stages utilize a loop-unrolled SAR structure for high-speed conversion. A 9-bit 500MS/s pipelined SAR ADC is fabricated in 28nm CMOS process, and it achieves SNDR of 49.1dB and SFDR of 60.4dB at low frequency and SNDR of 45.3dB and SFDR 56.0dB at Nyquist frequency. The measured performance over wide input common-mode and temperature range validates the operation of the replicabiased dynamic amplifiers. The measured Walden figure of merit (FoMw) is 23.3fJ/conversion-step and Schreier FoM (FoMs) is 158.6dB, respectively.INDEX TERMS Analog-to-digital converter (ADC), pipelined successive approximation resister (SAR), dynamic amplifier, replica-biasing.

The authors present a dither-less background digital bit weights calibration method for split-capacitor digital-to-analog converter (CDAC) successive approximation register (SAR) analog-to-digital converters (ADCs) to improve non-linearities caused by capacitor mismatch and bridge-capacitor inaccuracy errors in a split-CDAC. By using a digital pseudo-random number (PN) generator and paired comparators with opposite offsets, a dither-less background calibration quickly reaches the target signal-to-noise-and-distortion ratio (SNDR) within 5 × 10 4 samples for various process uncertainties. The simulated performance using a behavioural 6-bit + 6-bit ADC with 1-bit redundancy for various random offset and capacitor mismatches shows that the SNDR increases from 45.7 to 65.7 dB after the calibration.