This paper presents a 9-bit pipelined successive-approximation-register (SAR) ADC consisting of 4-stage sub-SAR ADCs using replica-biased dynamic residue amplifiers. The replica-biased amplifier in the 1st stage keeps the output common mode constant over various input voltage conditions, which enables cascading multiple dynamic-amplifier-based pipeline stages. The replica-biased amplifiers from the 2nd to the last stage maintain the differential gain, eliminating the need for bit-weight calibrations. The 1st~3rd stages utilize a loop-unrolled SAR structure for high-speed conversion. A 9-bit 500MS/s pipelined SAR ADC is fabricated in 28nm CMOS process, and it achieves SNDR of 49.1dB and SFDR of 60.4dB at low frequency and SNDR of 45.3dB and SFDR 56.0dB at Nyquist frequency. The measured performance over wide input common-mode and temperature range validates the operation of the replicabiased dynamic amplifiers. The measured Walden figure of merit (FoMw) is 23.3fJ/conversion-step and Schreier FoM (FoMs) is 158.6dB, respectively.INDEX TERMS Analog-to-digital converter (ADC), pipelined successive approximation resister (SAR), dynamic amplifier, replica-biasing.

This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling rate, with OSR of 7. The total power consumption of the ADC is 4.27 mW at a 1.1-V supply. The is 174.6 dB. The proposed structure achieves high resolution and wide bandwidth with good energy efficiency.

This paper presents an optimal digital filtering technique to enhance the resolution of incremental delta-sigma modulators (incremental DSMs, IDSMs) using a low-power passive integrator. We first describe a link between a passive integrator and its impact on the output of the IDSM. We then show that the optimal digital filter design can be cast as a convex optimization problem, which can be efficiently solved. As a test vehicle of the proposed technique, we use a behavioral 2nd-order IDSM model that captures critical non-idealities of the integrator, such as gain compression and output saturation. The effectiveness of the presented technique is verified using extensive simulations. The result shows that the presented filtering technique improves signal-to-noise and distortion ratio (SNDR) by 15 dB–20 dB, achieving SNDR over 90 dB when the oversampling ratio (OSR) = 256, and this corresponds to best-in-class performance when compared to previously published DSM designs using passive integrators.

The authors present a dither-less background digital bit weights calibration method for split-capacitor digital-to-analog converter (CDAC) successive approximation register (SAR) analog-to-digital converters (ADCs) to improve non-linearities caused by capacitor mismatch and bridge-capacitor inaccuracy errors in a split-CDAC. By using a digital pseudo-random number (PN) generator and paired comparators with opposite offsets, a dither-less background calibration quickly reaches the target signal-to-noise-and-distortion ratio (SNDR) within 5 × 10 4 samples for various process uncertainties. The simulated performance using a behavioural 6-bit + 6-bit ADC with 1-bit redundancy for various random offset and capacitor mismatches shows that the SNDR increases from 45.7 to 65.7 dB after the calibration.

This paper presents an electrochemical impedance spectroscopy (EIS) system-on-chip in 0.18-μm CMOS, achieving a wide scan frequency range of 1.25 MHz. An on-chip direct digital frequency synthesizer generates a digital sine wave as well as in-phase and quadrature-phase clocks that are synchronized to the sinewave. A chopped sampling mixer realizes lock-in detection without requiring quadrature sinewaves while suppressing low-frequency noise and offset. The receive utilizes a 12-bit pipelined SAR ADC operating in 5 MS/s in combination with a digital averaging filter to maximize the dynamic range. The measured performance shows that the prototype EIS chip achieves the highest frequency scan range with a comparable dynamic range of 108 dB and power consumption of 14 mW when compared with the previous state-of-the-art prototypes.