A PUF-Enabled Secure Architecture for FPGA-Based IoT Applications

Johnson, Anju P.; Chakraborty, Rajat Subhra; Mukhopadhyay, Debdeep

doi:10.1109/tmscs.2015.2494014

Cited by 70 publications

(35 citation statements)

References 20 publications

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“…FPGA based security solutions are quite prominent and widely adopted due to reconfigurability. Therefore, light-weight and secure cryptographic algorithms have been implemented on FPGA, and employed for the IoT security [24].…”

Section: Introductionmentioning

confidence: 99%

Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness

2019

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The physical unclonable functions (PUF) are used to provide software as well as hardware security for the cyber-physical systems. They have been used for performing significant cryptography tasks such as generating keys, device authentication, securing against IP piracy, and to produce the root of trust as well. However, they lack in reliability metric. We present a novel approach for improving the reliability as well as the uniqueness of the field programmable gated arrays (FPGAs) based ring oscillator PUF and derive a random number, consuming very small area (< 1%) concerning look-up tables (LUTs). We use frequency profiling method for distributing frequency variations in ring oscillators (RO), spatially placed all across the FPGA floor. We are able to spot suitable locations for RO mapping, which leads to enhanced ROPUF reliability. We have evaluated the proposed methodology on Xilinx -7 series FPGAs and tested the robustness against environmental variations, e.g. temperature and supply voltage variations, simultaneously. The proposed approach achieves significant improvement (i) in uniqueness value upto 49.90%, within 0.1% of the theoretical value (ii) in the reliability value upto 99.70%, which signifies that less than 1 bit flipping has been observed on average, and (iii) in randomness, signified by passing NIST test suite. The response generated through the ROPUF passes all the applicable relevant tests of NIST uniformity statistical test suite.

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Section: Introductionmentioning

confidence: 99%

Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness

2019

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“…Xilinx Zedboard, All Programmable SoC, were used to do this experiment [16]. Three IP Cores-OLED, s1423 Benchmark IP and a Full Adder IP -were used in this design.…”

Section: Methodsmentioning

confidence: 99%

“…The unit price is lower compared to the normal expensive license fees. An Internet of Things architecture which facilitates run-time modifications to the hardware components is described by Anju P Johnson [16]. This Partially Reconfigurable FPGA architecture is inspired from the principles of hardware sharing and hardware mixing.…”

Section: Review Of Literaturementioning

confidence: 99%

Hardware Signature Generation Using a Hybrid PUF and FSM Model for an SoC Architecture

Kokila

Das

Begum

et al. 2019

Period. Polytech. Elec. Eng. Comp. Sci.

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Security is becoming an important issue in the recent System on Chip (SoC) design due to various hardware attacks that can affect manufacturers, system designers or end users. Major issues include hardware Trojan attack, hardware intellectual property (IP) theft, such as an illegal sale or use of firm intellectual property cores or integrated circuits (ICs) and physical attacks. A hybrid model consisting of Arbiter PUF and Butterfly PUF are used to generate random responses which are fed to a Finite State Machine (FSM). A three-level FSM was designed to generate the signature correctly to authenticate IPs. The results were obtained with the help of three Intellectual Property (IP) cores – Zedboard OLED IP, ISCAS’89 s1423 Benchmark IP and a Full Adder IP. A 16-bit arbiter PUF and Butterfly PUF have been implemented on a 28nm FPGA. The average execution time to generate hardware signature for three IP cores was found to be 4.78 seconds (5 iterations) which is considerably low.

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“…To avoid DPR being exploited by attacks, and to permit its advantages to the fullest possible extent, careful protocol design to transfer only trusted DPR bitstreams to the FPGA is needed as well. A security protocol for unrestricted DPR usingPhysical Unclonable Functions (PUFs) for FPGA authentication and bitstream validation is a wise choice [27]. Our future research efforts would be directed towards designing a secure IoT protocol that permits unrestricted DPR to be performed on the system.…”

Section: Countermeasures Against the Proposed Attackmentioning

confidence: 99%

Remote dynamic partial reconfiguration: A threat to Internet-of-Things and embedded security applications

Johnson

Patranabis

Chakraborty

et al. 2017

Microprocessors and Microsystems

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The advent of the Internet of Things has motivated the use of Field Programmable Gate Array (FPGA) devices with Dynamic Partial Reconfiguration (DPR) capabilities for dynamic non-invasive modifications to circuits implemented on the FPGA. In particular, the ability to perform DPR over the network is essential in the context of a growing number of Internet of Things (IoT)-based and embedded security applications. However, the use of remote DPR brings with it a number of security threats that could lead to potentially catastrophic consequences in practical scenarios. In this paper, we demonstrate four examples where the remote DPR capability of the FPGA may be exploited by an adversary to launch Hardware Trojan Horse (HTH) attacks on commonly used security applications. We substantiate the threat by demonstrating remotely-launched attacks on Xilinx FPGA-based hardware implementations of a cryptographic algorithm, a true random number generator, and two processor based security applications -namely, a software implementation of a cryptographic algorithm and a cash dispensing scheme. The attacks are launched by on-the-fly transfer of malicious FPGA configuration bitstreams over an Ethernet connection to perform DPR and leak sensitive information. Finally, we comment on plausible countermeasures to prevent such attacks.

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A PUF-Enabled Secure Architecture for FPGA-Based IoT Applications

Cited by 70 publications

References 20 publications

Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness

Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness

Hardware Signature Generation Using a Hybrid PUF and FSM Model for an SoC Architecture

Remote dynamic partial reconfiguration: A threat to Internet-of-Things and embedded security applications

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