A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for a Tri-Mode GSM-EDGE/UMTS/DVB-T Receiver

Ho, Chen-Yen; Chan, Wei-Shan; Lin, Yung-Yu; Lin, T. H.

doi:10.1109/jssc.2011.2164026

Cited by 26 publications

(6 citation statements)

References 19 publications

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“…TABLE V compares the presented quadrature band-pass continuous-time (CT) ΣΔ modulator with the-state-of-the-art QBP CT ΣΔ modulators. [4] and [7] support multi-mode operations and only the maximum bandwidth modes are listed. Besides, the IRR in [4] is the result with the digital-calibration after the output of the modulator.…”

Section: Measured Resultsmentioning

confidence: 99%

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A 10-b Fourth-Order Quadrature Bandpass Continuous-Time $\Sigma \Delta $ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver

Zhang

et al. 2017

IEEE Trans. Microwave Theory Techn.

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A 4 th -order quadrature bandpass (QBP) continuous -time (CT) sigma-delta (ΣΔ) modulator for a dual-channel global navigation satellite system (GNSS) receiver is presented. With a bandwidth of 33 MHz, the modulator is able to digitalize the down-converted GNSS signals in two adjacent signal bands simultaneously, realizing dual-channel GNSS reception with one receiver channel instead of two independent receiver channels. To maintain the loop-stability of the high-order architecture, any extra loop phase shifting should be minimized. In the system architecture, a feedback and feedforward hybrid architecture is used to implement the 4 th -order loop-filter, and a return-to-zero (RZ) feedback after the discrete-time differential operation is introduced into the input of the final integrator to realize the excess loop delay (ELD) compensation, saving a spare summing amplifier. In the circuit implementation, power-efficient amplifiers with high-frequency active feedforward and antipole-splitting techniques are employed in the active RC integrators, and self-calibrated comparators are used to implement the low-power 3-bit quantizers. These power saving techniques help achieve superior figure of merit (FoM) for the presented modulator. With a sampling rate of 460 MHz, currentsteering digital-analog converters (DACs) are chosen to guarantee high conversion speed. Implemented in only 180 nm CMOS, the modulator achieves 62.1 dB peak Signal to Noise and Distortion Ratio (SNDR), 64 dB dynamic range (DR) and 59.3 dB image rejection ratio (IRR), with a bandwidth of 33 MHz, and consumes 54.4 mW from a 1.8 V power supply.

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Section: Measured Resultsmentioning

confidence: 99%

“…In [3]- [5] and [7], an active feedforward path realized with a differential pair is used to guarantee the phase margin. The differential pair is connected to the output while its gates are connected to the input.…”

Section: ) Power-efficient Amplifiermentioning

confidence: 99%

A 10-b Fourth-Order Quadrature Bandpass Continuous-Time $\Sigma \Delta $ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver

Zhang

et al. 2017

IEEE Trans. Microwave Theory Techn.

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“…The low-IF receiver (RX) architecture with modulators ( M) is a suitable solution for multi-standard operation due to its high reconfigurability (L. and a high dynamic range (DR). The high DR relaxes the requirements of the analog front-end (Ho et al, 2011) by reducing the need for high gain as well as a fine tuning of analog gain. Even coarse gain steps in the RF front-end ensure a sufficient signal level at the analog-digital converter (ADC) input and the sensitivity specifications for a standard like IEEE 802.15.4 (2016) can be fulfilled.…”

Section: Introductionmentioning

confidence: 99%

A digital receiver signal strength detector for multi-standard low-IF receivers

et al. 2018

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Abstract. This paper presents a receiver signal strength detector based on a discrete Fourier transform implementation. The energy detection algorithm has been designed and measured using a custom multi-standard transceiver ASIC with a low-IF receiver at 0.5, 1 and 2 MHz IF. The proposed implementation directly processes the single bit ΔΣ modulator data and features a clear channel assessment for arbitrary modulation schemes without energy consuming demodulation. Continuous monitoring of the derivative of the RSSI takes advantage of faster coefficient convergence for higher power levels and reduces computation time. A dynamic range of 65 dB has been achieved in FPGA based measurements with a linearity error of less than 1.2 dB. Furthermore, synthesis results for an on-chip implementation for an 130 nm RF CMOS technology show an overall power consumption of 1.5 mW during calculation.

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“…To achieve the desired signal channel selection and high image-rejection ratio (IRR), highorder IF complex bandpass filter is usually adopted, however, it would consume considerably large power. Due to its complex bandpass anti-aliasing characteristic, high dynamic range (DR) and potential for low power consumption, the continuous-time quadrature bandpass sigma-delta (CT QBP ) modulator is currently applied in low-IF multi-standard receivers [1]- [3], which could relax the requirements on the IF filter and amplifiers, therefore lowering the power consumption of the whole receiver.…”

Section: Introductionmentioning

confidence: 99%

“…The mismatch between I and Q channel would also lead to SNDR degradation [1] and emerge the image signal, and several techniques, such as quadrature mismatch scrambler (QMS) [3], inserted between the quantizer and multi-bit digital-to-analog converter (DAC), are proposed to improve the IRR, but it would contribute more ELD and increase the complexity of switches in DACs.…”

Section: Introductionmentioning

confidence: 99%

A 5/20MHz-BW 4.2/8.1mW CT QBP ΣΔ modulator with digital I/Q calibration for GNSS receivers

Zhang

et al. 2013

2013 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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This paper presents a dual-mode 2 nd -order, multi-bit reconfigurable continuous-time quadrature bandpass sigmadelta (CT QBP ) modulator employing power scaling technique (PST) for low-IF GNSS receivers. The proposed modulator is capable of supporting both narrow band (NB) of 5MHz bandwidth (BW) and wideband (WB) of 20MHz BW with sampling frequencies of 160MHz and 480MHz, respectively. To solve the instability issue caused by the excess loop delay (ELD) in WB mode, an additional DAC is directly feedback to the input of a summing amplifier and the ELD is fixed to half of the sampling period. Digital I/Q calibration after the decimation is employed to improve the image-rejection ratio (IRR). Implemented in 65nm CMOS, the modulator achieves 65.9/53.7dB SNDR, 76.7/65.9dB SFDR and more than 60dB IRR after calibration across 5/20MHz BW with center frequencies of 4/12MHz. Powered by a 1.2-V supply, the modulator consumes 3.5/6.8mW, resulting in FOMs of 264/516fJ/conversion.

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A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for a Tri-Mode GSM-EDGE/UMTS/DVB-T Receiver

Cited by 26 publications

References 19 publications

A 10-b Fourth-Order Quadrature Bandpass Continuous-Time $\Sigma \Delta $ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver

A 10-b Fourth-Order Quadrature Bandpass Continuous-Time $\Sigma \Delta $ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver

A digital receiver signal strength detector for multi-standard low-IF receivers

A 5/20MHz-BW 4.2/8.1mW CT QBP ΣΔ modulator with digital I/Q calibration for GNSS receivers

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A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for a Tri-Mode GSM-EDGE/UMTS/DVB-T Receiver

Cited by 26 publications

References 19 publications

A 10-b Fourth-Order Quadrature Bandpass Continuous-Time $\Sigma \Delta $ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver

A 10-b Fourth-Order Quadrature Bandpass Continuous-Time $\Sigma \Delta $ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver

A digital receiver signal strength detector for multi-standard low-IF receivers

A 5/20MHz-BW 4.2/8.1mW CT QBP &#x03A3;&#x0394; modulator with digital I/Q calibration for GNSS receivers

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Product

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A 5/20MHz-BW 4.2/8.1mW CT QBP ΣΔ modulator with digital I/Q calibration for GNSS receivers