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This paper presents a power-efficient single-loop continuous-time (CT) modulator (DSM) that achieves a SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modulator uses a fourth-order feed-forward architecture incorporating the continuous-time self-coupling (CTSC) technique. Moreover, to reduce hardware area, this design utilizes the residual signal for excess loop delay (ELD) compensation. To improve linearity, low-ripple DAC latches and low toggle-rate dynamic element matching (DEM) algorithm are adopted. This DSM is fabricated in a 55 nm LP CMOS technology. Operating at 140 MHz sampling rate, the chip consumes 4.5 mW from power supplies of 1.2 V and 1.8 V. It achieves 90.4 dB SNDR and 92 dB dynamic range (DR) with a 2.2 MHz signal bandwidth, resulting in a Schreier FOM of 177.3 dB and 178.9 dB based on SNDR and DR, respectively. The chip area is 0.09 mm .

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A high-dynamic-range (DR) CT ΔΣ modulator is required to relax the analog front-end filter design for wireless communication applications. To achieve high resolution (DR>90dB) and low power dissipation (FoMs>170dB), architecture selection and circuit techniques are the main design issues. In [1], a CT ΔΣ modulator embedded with a 2 nd -order active filter and VGA is reported to extend the DR. However, the additional active filter results in a complicated architecture as well as extra area that is not preferred in advanced processes. An alternative method that improves the DR is to adopt the self-coupled noise-injection technique introduced in [2] to increase by one the order of the noise transfer function (NTF). Unfortunately, it requires an accurate clock cycle delay, which is only available in the DT ΔΣ modulator. Apart from DR considerations, power efficiency is still limited by the building block design. Conventional excess loop delay (ELD) compensation [1,3,4] is implemented by an inner DAC, which increases the power consumption and loads the last integrator with a large parasitic capacitance, especially for a multi-bit modulator. Therefore, a high-bandwidth opamp is required in the last integrator to alleviate the phase delay of the loop filter. Furthermore, to address the nonlinearity of a multi-bit DAC, 2 nd -order dynamic element matching (DEM) is used in [5] to reduce data-dependent switching. The SFDR is still limited to 90dB. In this paper, CT self-coupling (CTSC), residual ELD compensation, and DAC linearity enhancement techniques are introduced to overcome these challenges. Our CT ΔΣ modulator achieves an SNDR of 90.4dB with an FoMs (SNDR) of 177.3dB in a 2.2MHz bandwidth.In Fig. 15.2.1 (a), the modulator, clocked at 140MHz, employs a 4 th -order feed-forward (FF) architecture with a 4b asynchronous successiveapproximation register (ASAR) quantizer (QTZ) [3] and advancing data-weighted averaging (ADWA) [6]. The high-gain loop filter provides strong noise-shaping capability to suppress the noise and nonlinearity at the back-end stages. The high-speed FF path for the S -1 term [4], realized by R f4 and R 4 , is used for robust stability. The CTSC technique is used to enhance the SQNR since the selfcoupling path forms an additional 1 st -order integrator. In the last integrator, the positive feedback implemented by C 4 and R 5 provides a 2 nd -order transfer function. The equivalent linear model is shown in Fig. 15.2.1 (b). To realize the self-coupling in the S-domain, Z -1 is transformed to 1/(1+KS), where K is determined by the coefficient synthesis. To reuse the opamp in the last-stage integrator, S/(1+KS) is applied to keep the same transfer function as the self-coupling path. By choosing C 3 =C 4 , the SC term is cancelled. Therefore, the expression, 1/(1+KS) can be derived by the product of the transconductance part (C 4 R 5 ) and the integration path (C 3 ). With the CTSC technique, in-band SQNR is improved by an amount that depends on the loop filter order, OSR, and QTZ-bit number. In this wor...