A Quantitative Method for Measuring Remaining Silicon Thickness during XeF2 FIB Trenching for Backside Circuit Operations

Abstract

Backside circuit edit (CE) remains a crucial failure analysis (FA) capability, enabling design modifications on advanced integrated circuits. [1-9] A key requirement of this activity is to approach the active transistor layer of the silicon through the removal of the silicon substrate without exposing or damaging critical transistor features. Several methods have been previously developed to enable or assist with the process with either global or locally targeted techniques for thinning the silicon substrate. These methods employ mechanical methods, laser based techniques (continuous or pulsed), or chemical assisted focused ion beam (FIB) etching to accomplish the thinning. Each of these methods presents different strengths and weaknesses, from their reliability to complexity, but very few techniques provide a precise and accurate quantitative measure of the remaining silicon thickness (RST). Here, we will discuss the use of a FIB with XeF2 for backside Si removal, and the development of an in-situ, accurate measurement of RST.

Ultra-thin bulk silicon thinning of advanced microprocessors & graphics processors fabricated in Sub-20 nm technology

“…Due to the dependence on the gas precursor for etching, it is apparent that the etching characteristics and rate enhancements are dependent on the local XeF2 gas pressure on top of the other milling conditions. As such, silicon trenching operations typically involve moderate 200 μm x 200 μm trenches milled under specialized coaxial nozzles dispensing XeF2 for etching uniformity [34]. A point of consideration during GAE is thus the avoidance of gas depletion by balancing the sputter action against the etching rate during milling.…”