A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPC/sup TM/ microprocessor

Abstract

Static timing analysis tools are used by designers of high speedlhigh performance circuits to determine whether timing requirements are met. Timing analysis tools can report critical paths which are characterized by a transition on each node along the path, however, they cannot generate a "witness" vector which would sensitize that path. This gives rise to the possibility of having paths which are reported by the static timing analysis tool as potential critical paths, whereas there exists no vector sequence which can sensitize them. Our goal is to identify these "false critical timing paths" safely and without much overhead, so that the efforts needed to redesign and/or optimize critical paths can be reduced. We have devised a simple technique using a tool that we have written and a commercial ATPG tool to meet this goal. We applied the technique on the state of the art fourth generation MPC7400 PowerPC' microprocessor [3] designed at Motorola's PowerPC Design Center in Austin, TX. Our initial experimental results show the effectiveness of the technique. The salient features of the technique are that it is both quick and inexpensive.

False timing path identification using ATPG techniques and delay-based information

“…Earlier results in [6] [9] demonstrate the effectiveness of ATPG techniques. Since they are not BDD-based, the problems with BDD blow-ups while analyzing timing paths for a full chip are not encountered.…”