A Radiation Hardened by Design Register File With Lightweight Error Detection and Correction

Mohr, K.C.; Samson, G.; Clark, Lawrence T.

doi:10.1109/tns.2007.903173

Cited by 11 publications

(4 citation statements)

References 15 publications

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“…The simulation result has been contrasted with several published reliability models (Li, 2013;Saleh, 1990), which is shown in Figure 6. In Figure 6, no SEC is that register file is free of any ECC code protection and SEC no scrubbing means ECC protection but without scrubbing Slegel, 1999;Mohr, 2007). The SEC with scrubbing is ECC protection and with Figure 6.…”

Section: Discussion Of Resultsmentioning

confidence: 99%

“…The half-custom register file is easily constructed based on memory library from semiconductor technology vendors (Aeroflex, 2014), which usually cooperates with error correcting code (ECC), scrubbing and bit interleaving to improve security and reliability of register file. The ECC and lightweight ECC coding are used to correct the data error in the half-custom register file, which does not work yet once the error accumulation exceeds ECC error correction and detection ability Slegel, 1999;Mohr, 2007). Gaisler and Wang present some enhanced reliability methods based on pipeline restart.…”

Section: Introductionmentioning

confidence: 99%

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Method for Improving Data Security in Register Files Based on Multiple Pipeline Restart

Chen

et al. 2015

International Journal of Information Technology and Web Engineering

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Data security in the register file significantly decreases as a result of technology scaling. Based on pipeline restart, the method of improving the data security and reliability in register files is presented in this paper. As the data and its replica simultaneously exist as a redundant copy of each other in half-custom register files, when an uncorrectable error is detected in the data during the access of the register file, its replica will be checked for subsequent processor operation by the restart of pipeline. In addition, the correctable error in data or its replica can also be scrubbed by rollback and restart of pipeline. Finally, the proposed method is evaluated and the results show that the hardware overhead increases by only 2%, whereas the reliability of data in register file increases by more than 2.5 times. This method can significantly improve the data security in the register file without distinct overhead increasing.

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Section: Discussion Of Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Method for Improving Data Security in Register Files Based on Multiple Pipeline Restart

Chen

et al. 2015

International Journal of Information Technology and Web Engineering

View full text Add to dashboard Cite

show abstract

“…Of course, there is associated overhead (area, power, speed, etc.). System level approaches, such as Error Detect and Correction (EDAC) 19,20 generally manage errors (as opposed to eliminating them), often involving software and dedicated circuitry. However the efficacy of these techniques depends on the expected frequency of errors they are expected to deal with.…”

Section: Mitigationmentioning

confidence: 99%

Single Event Effects in the Nano Era

Alles¹,

Massengill²,

Schrimpf³

et al. 2008

Int. J. Hi. Spe. Ele. Syst.

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Scaling of complementary metal oxide semiconductor (CMOS) technologies to the sub-100 nm dimension regime increase the sensitivity to pervasive terrestrial radiation. Diminishing levels of charge associated with information in electronic circuits, interactions of multiple transistors due to tight packing densities, and high circuit clock speeds make single event effects (SEE) a reliability consideration for advanced electronics. The trend to adapt and apply commercial IC processes for space and defense applications has provided a catalyst to the development of infrastructure for analysis and mitigation that can be leveraged for advanced commercial electronic devices. In particular, modeling and simulation, leveraging the dramatic reduction in computing cost and increase in computing power, can be used to analyze the response of electronics to radiation, to develop and evaluate mitigation approaches, and to calculate the frequency of problematic events for target applications and environments. Int. J. Hi. Spe. Ele. Syst. 2008.18:815-824. Downloaded from www.worldscientific.com by NANYANG TECHNOLOGICAL UNIVERSITY on 08/21/15. For personal use only. 816 M. L. Alles et al.

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“…Soft errors caused by high-energy particle strikes have been known as a serious reliability threat in the space applications [19] [20]. As technology shrinks toward nanometer era, soft errors are becoming a serious reliability challenge in ground-level applications too [7] [8].…”

Section: Introductionmentioning

confidence: 99%

An efficient technique to tolerate MBU faults in register file of embedded processors

Abazari

Fazeli

Patooghy

et al. 2012

The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012)

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This paper presents a Data Width-aware Register file Protection (DWRP) technique to cope with Multiple Bit Upsets (MBUs) occurring in the register file of embedded processors. The DWRP technique has been proposed based on the fact that there are often a significant number of bits in the register file, which are not fully occupied by data. The DWRP technique efficiently exploits these available free bits for reliability enhancement purposes. In this regard, every register is equipped with three extra tag bits to specify the amount of available free bits in a register. Then the appropriate parity or hamming code is used based on the information of the tag field to protect the register file against MBUs. The DWRP technique is extensively evaluated on an HDL model of an ARM embedded processor along with various MBU fault injection experiments. Experimental results show that the DWRP technique detects up to 99% of MBUs with average length of 16 bits. These are achieved with negligible overheads of 7% in area and 1% in power consumption of the evaluated processor.

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A Radiation Hardened by Design Register File With Lightweight Error Detection and Correction

Cited by 11 publications

References 15 publications

Method for Improving Data Security in Register Files Based on Multiple Pipeline Restart

Method for Improving Data Security in Register Files Based on Multiple Pipeline Restart

Single Event Effects in the Nano Era

An efficient technique to tolerate MBU faults in register file of embedded processors

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