An efficient technique to tolerate MBU faults in register file of embedded processors

Abazari, Mustafa; Fazeli, Mahdi; Patooghy, Ahmad; Miremadi, Seyed Ghassem

doi:10.1109/cads.2012.6316430

Cited by 8 publications

(6 citation statements)

References 28 publications

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“…To avoid saving and restoring the whole system data, some hardware platforms already provide memory with safety and data protection mechanisms such as Error Correcting Code (ECC) and TMR-based memories, among others [19,31]. Therefore, and assuming that the Lock-V can resort to such memory systems, the great source of errors is likely to be from the processors' register file, one of the most critical parts of the processor [32][33][34][35][36]. These errors usually occur due to SEU that cause bit-flips problems.…”

Section: System Recoverymentioning

confidence: 99%

Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V

Marques

Rodrigues

Tavares

et al. 2021

Microelectronics Reliability

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Section: System Recoverymentioning

confidence: 99%

Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V

Marques

Rodrigues

Tavares

et al. 2021

Microelectronics Reliability

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“…The probability of MBU (multiple bit upset) generation due to SEU, is increasing because of the decreasing logic depth, reducing capacitance of nodes, lowering supply voltage, increasing the clock frequency of the system and high integration density [1] [7].…”

Section: Introductionmentioning

confidence: 99%

Fault tolerant register file design for MIPS AES-crypto microprocessor

Ustaoglu

Örs

2015

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

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This paper represents a new method to protect register file of a RISC microprocessor against MBUs. The key idea is combining the most important properties of two methods in the literature. One of them is a type of information redundancy called as matrix code that has detection and correction capability. The other one is TMR which is a widely used hardware redundancy technique and masks faults. The microprocessor has been designed as a 32-bit single cycle MIPS architecture. Moreover, a crypto module has been designed and integrated into the microprocessor and AES-128 algorithm is implemented in order to create an application platform. The proposed method can detect and correct up to 2, 4, 8-burst or random errors in any register based on the dataset configuration. This design has been implemented in Xilinx Virtex-5 FPGA. Area and power consumption has been compared. The method is applicable for register files with different sizes.

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“…In [34], the Error Correction Codes is stored in the unused bits of a register to provide robustness. Another study presented the Data Width‐aware Register file Protection technique that copes with multiple bit upsets [35]. This technique is based on the fact that all bits of a register do not contain data.…”

Section: Introductionmentioning

confidence: 99%

Micro‐architectural approach to the efficient employment of STTRAM cells in a microprocessor register file

Asgari

Fazeli

Patooghy

et al. 2016

IET Computers & Digital Techniques

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In this paper, the authors propose two approaches that employ spin transfer torque random access memory (STTRAM) in the design of the register file, an important part of embedded processors. However, STTRAM suffers from both endurance and latency in the write operation. Consequently, employing STTRAM in the register file entails two challenges: (i) the lifetime significantly decreases as data are frequently written into a register file; (ii) the delay of the critical path increases as a result of the slow write operation. They have proposed using two well‐known micro‐architectural approaches: the last‐write‐update (LWU) and the value locality (VL), to minimize the number of write operations into a register. The main observation behind LWU is that only the last write operations of certain registers in the re‐order buffer should be considered. VL exploits the fact that a limited number of values are more likely to be written into a register file. Their simulation shows that by employing the LWU and VL approaches, the lifetime of the STTRAM‐based register file, compared with the lifetime of traditional static RAM‐based register file architecture, extends to about 40 years on average and around 3.5 years in the worst case while improving power consumption by 30%.

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An efficient technique to tolerate MBU faults in register file of embedded processors

Cited by 8 publications

References 28 publications

Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V

Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V

Fault tolerant register file design for MIPS AES-crypto microprocessor

Micro‐architectural approach to the efficient employment of STTRAM cells in a microprocessor register file

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