This paper represents a new method to protect register file of a RISC microprocessor against MBUs. The key idea is combining the most important properties of two methods in the literature. One of them is a type of information redundancy called as matrix code that has detection and correction capability. The other one is TMR which is a widely used hardware redundancy technique and masks faults. The microprocessor has been designed as a 32-bit single cycle MIPS architecture. Moreover, a crypto module has been designed and integrated into the microprocessor and AES-128 algorithm is implemented in order to create an application platform. The proposed method can detect and correct up to 2, 4, 8-burst or random errors in any register based on the dataset configuration. This design has been implemented in Xilinx Virtex-5 FPGA. Area and power consumption has been compared. The method is applicable for register files with different sizes.

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Özetçe -Bu çalışmada iş hatlı MIPS-32 mikroişlemcisinin hataların varlıgında düzgün birşekilde çalışmasına devam edebilmesi için çeşitli hata bagışıklık yöntemleri ele alınmış ve güvenilirlik analizleri yapılmıştır. Mikroişlemcinin en önemli birimlerinden biri olan kaydedici dosyasına odaklanılmıştır. Bu yöntemlerle tasarlanan kaydedici dosyaları Cadence RTL Compiler'da TSMC 90nm'de sentezlenmiştir. Hataların Poisson dagılımıyla oluştugu ve bit bozulmalarının istatistiksek olarak birbirinden bagımsız oldugu varsayılarak güvenilirlik analizleri için matematiksel model oluşturulmuştur. Octave programı ile elde edilen kaydedici dosyalarının güvenilirlik analiz sonuçları verilmiştir.Anahtar Kelimeler-güvenilirlik, hata bagışıklık yöntemleri, mikroişlemci, kaydedici dosyası, üçlü modül çogullama.Abstract-In this study, various fault tolerant techniques have been handled for pipelined MIPS-32 microprocessor in order for correct operation in the presence of faults and reliability analysis have been performed. For this purpose, register file is focussed on due to the fact that it is one of the most important unit of microprocessor. Register files designed with the fault tolerant methods have been synthesized with Cadence RTL Compiler, area and maximum frequency results have been obtained based on TSMC-90 nm technology. Mathematical models have been presented with the assumption that transient faults occur with a Poisson distribution and bit failures are statistically independent for reliability analysis. The results and graphics have been given by using Octave.

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