Design and implementation of a custom verification environment for fault injection and analysis on an embedded microprocessor

Ustaoglu, Buse; Örs, Berna

doi:10.1109/taeece.2015.7113636

Cited by 3 publications

(2 citation statements)

References 6 publications

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“…Control inputs are for transient injection and range from 001 50% injection to 110 1% injection. A control input of 000 means no fault injection while a control code of 111 is 100% that is to say permanent fault injection [13].…”

Section: Experimental Setup and Resultsmentioning

confidence: 99%

Fault tolerant register file design for MIPS AES-crypto microprocessor

Ustaoglu

Örs

2015

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

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This paper represents a new method to protect register file of a RISC microprocessor against MBUs. The key idea is combining the most important properties of two methods in the literature. One of them is a type of information redundancy called as matrix code that has detection and correction capability. The other one is TMR which is a widely used hardware redundancy technique and masks faults. The microprocessor has been designed as a 32-bit single cycle MIPS architecture. Moreover, a crypto module has been designed and integrated into the microprocessor and AES-128 algorithm is implemented in order to create an application platform. The proposed method can detect and correct up to 2, 4, 8-burst or random errors in any register based on the dataset configuration. This design has been implemented in Xilinx Virtex-5 FPGA. Area and power consumption has been compared. The method is applicable for register files with different sizes.

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Section: Experimental Setup and Resultsmentioning

confidence: 99%

Fault tolerant register file design for MIPS AES-crypto microprocessor

Ustaoglu

Örs

2015

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

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“…BuseUstaoglu et.al. [13] A fault in a single piece in the microprocessors may bring about delicate blunders. It has diverse effects on the program result whether the fault changes a circumstance in the application.…”

Section: Literature Reviewmentioning

confidence: 99%