Micro‐architectural approach to the efficient employment of STTRAM cells in a microprocessor register file

Abstract

In this paper, the authors propose two approaches that employ spin transfer torque random access memory (STTRAM) in the design of the register file, an important part of embedded processors. However, STTRAM suffers from both endurance and latency in the write operation. Consequently, employing STTRAM in the register file entails two challenges: (i) the lifetime significantly decreases as data are frequently written into a register file; (ii) the delay of the critical path increases as a result of the slow write operation. They have proposed using two well‐known micro‐architectural approaches: the last‐write‐update (LWU) and the value locality (VL), to minimize the number of write operations into a register. The main observation behind LWU is that only the last write operations of certain registers in the re‐order buffer should be considered. VL exploits the fact that a limited number of values are more likely to be written into a register file. Their simulation shows that by employing the LWU and VL approaches, the lifetime of the STTRAM‐based register file, compared with the lifetime of traditional static RAM‐based register file architecture, extends to about 40 years on average and around 3.5 years in the worst case while improving power consumption by 30%.