A radiation hardened reconfigurable FPGA

Ramaswamy, S.; Rockett, L.; Patel, D.; Danziger, Steven; Manohar, Rajit; Kelly, Clinton W.; Holt, John Lofton; Ekanayake, Virantha; Elftmann, Dan

doi:10.1109/aero.2009.4839506

Cited by 16 publications

(17 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For example, the first, second, and third FF in the top synchronous pipeline get mapped into the first, fourth, and fifth RX/TX pairs respectively in the bottom picoPIPE pipeline. These RX/TX pairs have fault-tolerance built into them using redundancy voting [15]. There are 0, 4, and 8 stages of inversion between each flip-flop, and there can be a variable number of routing hops on each path between the individual inversion stages and flops.…”

Section: A Test Backgroundmentioning

confidence: 99%

See 1 more Smart Citation

Mitigation of Single-Event Charge Sharing in a Commercial FPGA Architecture

Kelly

Alles

Ball

et al. 2014

IEEE Trans. Nucl. Sci.

Self Cite

View full text Add to dashboard Cite

The motivation for single event effects (SEE) analysis and mitigation as part of the process for adaptation of a commercial Field Programmable Gate Array (FPGA) architecture for space-qualified applications is discussed. The interdependent roles of heavy-ion and laser-induced upset evaluation coupled with computer-aided investigations of SEE mechanisms and mitigation techniques in this process are shown to enable a significant reduction in SEE sensitivity of the device, while achieving minimal impact on remanufacturing steps.Index Terms-Charge sharing, radiation hardening by design, RHFGPA, single event effects.

show abstract

Section: A Test Backgroundmentioning

confidence: 99%

“…The FPGA combines a synchronous IO interface with an asynchronous picoPIPE core, where handshake protocols and explicit data token transmission between reconfigurable logic blocks (RLBs) encode synchronization/validation signals within the data [15].…”

Section: A Backgroundmentioning

confidence: 99%

Mitigation of Single-Event Charge Sharing in a Commercial FPGA Architecture

Kelly

Alles

Ball

et al. 2014

IEEE Trans. Nucl. Sci.

Self Cite

View full text Add to dashboard Cite

show abstract

“…However, there are some successful examples reported in recent literature, e.g. the Opus2 family of asynchronous DSP multiprocessors from Octasic Inc. [8] and high speed FPGAs from Achronix, Inc. [9].…”

Section: Introductionmentioning

confidence: 98%

LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries

Moreira

Oliveira

Calazans

et al. 2013

2013 Euromicro Conference on Digital System Design

View full text Add to dashboard Cite

Semi-custom design flows are a key factor for the rapid growth of integrated circuits and systems. They lower design complexity through the use of pre-designed and precharacterized functional components called standard cells, instead of assuming that designers have to draw, place and connect each transistor. In this way, modeling of complex systems is easier. As CMOS technologies evolve into deep submicron nodes, asynchronous techniques gain relevance in the research community, due to their ability to cope with problems that are hard to solve with the synchronous paradigm. However, several specific components required in asynchronous designs are not available in commercial standard cell libraries, which constrains asynchronous design to use approaches close to full-custom ones. This limits modularity and increases design complexity. Thus, one of the possibilities for enabling further advance of the asynchronous paradigm is the availability of asynchronous standard cell libraries. Albeit industrial tools provide reasonable support to asynchronous standard cells physical design, the characterization of these cells using standard tools is usually quite laborious. This work proposes the Library Characterization Environment (LiChEn), an open source tool applicable to automatically characterize typical asynchronous standard cells. The tool managed to successfully characterize a standard cell library with over five hundred asynchronous components.

show abstract

“…The filters implemented on conventional synchronous hardware is extended to the emerging logic design paradigm of clock free asynchronous quasi delay insensitive (a-QDI) circuits. We compare using Achronix devices [2], [3], the relative speeds of a-QDI logic circuits and conventional synchronous circuits for hardware realization of two classes of raster-scanned (RS) 2D IIR algorithms [4]- [6]: 1) direct-form I signal flow graphs (SFGs) and 2) wavedigital filters (WDFs) [7] based on discretized S-parameters. By eliminating the global clock, the a-QDI logic leads to reduced design complexity, lower energy consumptions, and higher speeds of operation [8].…”

Section: Introductionmentioning

confidence: 99%

Asynchronous-QDI 2D IIR digital filter circuits

Rajapaksha

Madanayake

2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

This paper investigates the potential of emerging asynchronous quasi delay insensitive (a-QDI) logic devices for the realization of high-speed low-power 2D infinite impulse response digital beam filters. Recently proposed raster-scanned hardware architectures based on direct-form I and wave-digital realization are extended to clock-free asynchronous logic using state-of-the-art asynchronous field programmable gate arrays from Achronix Semiconductor. For the specific class of 2D IIR beam filters based on raster-scanned hardware, it is shown using extensive experimental work that direct-form I architectures greatly benefit from the adoption of a-QDI logic over standard clocked (synchronous) digital circuits while wave-digital filters show no difference in performance. To the author's knowledge, the proposed 2D IIR hardware circuits are currently the only available realization of 2D IIR filters in the literature based on the new clock-free a-QDI paradigm.

show abstract

A radiation hardened reconfigurable FPGA

Cited by 16 publications

References 1 publication

Mitigation of Single-Event Charge Sharing in a Commercial FPGA Architecture

Mitigation of Single-Event Charge Sharing in a Commercial FPGA Architecture

LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries

Asynchronous-QDI 2D IIR digital filter circuits

Contact Info

Product

Resources

About