A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture

Abstract

In this work, we present a radix-10 division unit that is based on the digit-recurrence algorithm. The previous decimal division designs do not include recent developments in the theory and practice of this type of algorithm, which were developed for radix-2 k dividers. In addition to the adaptation of these features, the radix-10 quotient digit is decomposed into a radix-2 digit and a radix-5 digit in such a way that only five and two times the divisor are required in the recurrence. Moreover, the most significant slice of the recurrence, which includes the selection function, is implemented in radix-2, avoiding the additional delay introduced by the radix-10 carry-save additions and allowing the balancing of the paths to reduce the cycle delay. The results of the implementation of the proposed radix-10 division unit show that its latency is close to that of radix-16 division units (comparable dynamic range of significands) and it has a shorter latency than a radix-10 unit based on the Newton-Raphson approximation.

Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

“…One of the fastest decimal fixed-point divider on ASICs is the design of Lang and Nannarelli [14]. They minimize the critical path in the digit recurrence by using a fast quotient digit selection function based on binary carry-propagate adders that subtract fixed values from the estimation of the current residual.…”

“…Lang and Nannarelli [14] replace the divisor's multiples by comparative values obtained by a look-up table and decompose the quotient digit into a radix-2 digit and a radix-5 digit in such a way that only five and two times the divisor are required. Vázquez et al [15] take a different approach: the selection constants in the QDS function are obtained of truncated multiples of the divisor, avoiding lookup tables.…”

“…Lang and Nannarelli [14] propose a divider that implements a quotient digit selection function based on CPAs and sign detection. These CPAs subtract fixed values from the current residual with limited precision.…”

Are Ieee 754 32-Bit and 64-Bit Binary Floating-Point Accurate Enough?

“…Then the hardware computes the x fraction bits as if they are integral values [2,14,[17][18]. The decimal fraction is gained by integral division, with the former divided by the latter.…”

“…Formula 2 exemplifies the case for x = 3. Finally that integral value is divided by 10 x [18]. In our example, the 125 is divided by 10 3 , the final result is 0.125 10 .…”