A random-access-memory cell based on quantum flux parametron with three control lines

Takayama, Hiromitsu; Takeuchi, Naoki; Yamanashi, Yuki; Yoshikawa, Nobuyuki

doi:10.1088/1742-6596/1054/1/012063

Cited by 7 publications

(3 citation statements)

References 20 publications

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“…Use of flux quantum in a superconducting loop to store data can match the speeds of SFQ circuits . Several types of memory cells like vortex transition memory and quantum flux parametron memory have been developed by tunneling Josephson junctions. − Recently, these cell dimensions were reduced to 9 × 11 μm 2 using a state-of-the-art Nb-based junction process developed at the MIT Lincoln Laboratory . Unfortunately, further cell area reduction will be extremely challenging because of the requirement for few-pH inductors.…”

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confidence: 99%

Miniaturization of the Superconducting Memory Cell via a Three-Dimensional Nb Nano-superconducting Quantum Interference Device

Chen

Wang

et al. 2020

ACS Nano

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Scalable memories that can match the speeds of superconducting logic circuits have long been desired to enable a superconducting computer. A superconducting loop that includes a Josephson junction can store a flux quantum state in picoseconds. However, the requirement for the loop inductance to create a bi-state hysteresis sets a limit on the minimal area occupied by a single memory cell. Here, we present a miniaturized superconducting memory cell based on a Three-Dimensional (3D) Nb nano-Superconducting QUantum Interference Device (nano-SQUID). The major cell area here fits within an 8×9 μm 2 rectangle with a cross-selected function for memory implementation. The cell shows periodic tunable hysteresis between two neighbouring flux quantum states produced by bias current sweeping because of the large modulation depth of the 3D nano-SQUID (~66%). Furthermore, the measured Current-Phase Relations (CPRs) of nano-SQUIDs are shown to be skewed from a sine function, as predicted by theoretical modelling. The skewness and the critical current of 3D nano-SQUIDs are linearly correlated. It is also found that the hysteresis loop size is in a linear scaling relationship with the CPR skewness using the statistics from characterisation of 26 devices. We show that the CPR skewness range of π/4-3π/4 is equivalent to a large loop inductance in creating a stable bi-state hysteresis for memory implementation. Therefore, the skewed CPR of 3D nano-SQUID enables further superconducting memory cell miniaturization by overcoming the inductance limitation of the loop area.

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confidence: 99%

Miniaturization of the Superconducting Memory Cell via a Three-Dimensional Nb Nano-superconducting Quantum Interference Device

Chen

Wang

et al. 2020

ACS Nano

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“…Superconducting memory has been developed in RSFQ [32][33][34] , RQL 35 , AQFP 36 , with an allsuperconducting memory achieving a density of up to 1 Mb/cm 2 , 37 and magnetic-enhanced memory research providing a route to higher density without further advancements in lithography 38 . The shift regis-ter, being more relevant here, is a fast memory for on chip with processing, related to "registers" and cache.…”

Section: G Discussionmentioning

confidence: 99%

Asynchronous Reversible Computing Unveiled Using Ballistic Shift Registers

Osborn¹,

Wustmann²

2022

Preprint

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Reversible logic has recently progressed in superconducting circuits and promises momentous improvements in computing efficiency relative to irreversible logic developed by industry in semiconductor circuits. Superconducting logic uses single flux quanta (SFQ) to represent bits, and unlike their irreversible SFQ-logic relatives the bits may switch state with extremely low dissipation. Here we propose and simulate ballistic shift registers (BSRs). These devices are reversible and dramatically more energy-efficient than previous ones, including a pioneering one developed before the advent of SFQ logic. The BSR is ballistic because no power is supplied to the gate other than the input bits themselves; the results are conveyed as slightly slower output bits. The BSR uses an SFQ of either polarity for the stored bit as well as ballistic fluxons. The BSR additionally uses shunt capacitors and the nonlinearity of the ends of long Josephson junctions to support partial fluxons and energy-conserving dynamics. The BSRs are multi-port and allow asynchronous bit arrivalimportant functionalities not available in previous reversible gates. During their interaction, the stored and the moving bits swap their bit states, resulting in the shift-register operation. We show that two BSRs operate in sequence without power added. In addition, we show that a BSR circuit with two inputs allows a bit state to be conveyed on different outputs. This constitutes the first asynchronous ballistic 2-input gate. Finally, for a more intuitive understanding of the dynamics, we introduce a collective coordinate model. It describes the 1-bit BSR dynamics with the motion of two coordinates in a potential determined by the states of the input bit and the initial stored SFQ. We discuss the potential for this SFQ logic type in the context of energy efficiency, parameter margins, logical depth, and speed.

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“…Other than the vortex transition cell, numerous other types of flux-based memory cells have also been developed previously [10][11][12][13][14]. New memory devices have been developed including based on magnetic junctions [15][16][17][18][19][20], f-Josephson junctions [21], photon modulated cells [22], superconducting frustration bits [23], hybrid magnetic cells [24], adiabatic quantum flux parametron cells [25], cells with 0-and p-junctions [26], integrated ferromagnetic and superconducting junction cells [27,28], spin-torque transfer cells [29].…”

Section: Introductionmentioning

confidence: 99%

Experimental demonstration of a Josephson cryogenic memory cell based on coupled Josephson junction arrays

Nair

Jafari-Salim

D’Addario

et al. 2019

Supercond. Sci. Technol.

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In this paper, experimental verification for a cryogenic memory cell consisting of three inductively coupled Josephson junctions is presented. Design and operational logic of this type of cell was recently introduced. The basic memory cell operations (read, write, reset) can be implemented on the same simple circuit and this type of memory cell is fundamentally different from the existing single flux quantum-based memory cells. Here, we present design principles and experimental validation for write operations and readout operation for four versions of the design, each with different parameters. Our experimental results show excellent resemblance with the previously presented memory cell operational logic and also show an excellent fit with simulations of the entire memory cell circuit that includes the memory cell and all the peripheral circuitry.

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A random-access-memory cell based on quantum flux parametron with three control lines

Cited by 7 publications

References 20 publications

Miniaturization of the Superconducting Memory Cell via a Three-Dimensional Nb Nano-superconducting Quantum Interference Device

Miniaturization of the Superconducting Memory Cell via a Three-Dimensional Nb Nano-superconducting Quantum Interference Device

Asynchronous Reversible Computing Unveiled Using Ballistic Shift Registers

Experimental demonstration of a Josephson cryogenic memory cell based on coupled Josephson junction arrays

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