A read disturbance free differential read SRAM cell for low power and reliable cache in embedded processor

Nayak, Debasish; Acharya, Debiprasad Priyabrata; Mahapatra, Kamalakanta

doi:10.1016/j.aeue.2017.02.012

Cited by 23 publications

(5 citation statements)

References 14 publications

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“…Static commotion edge (SNM) is the most well-known technique for estimating the solidness of a grasp of the cell [20], [21]. Strength adjustment is resolved when the SRAM cell is in the standing firm on situation.…”

Section: Hold Stabilitymentioning

confidence: 99%

Restoration circuits for low power reduce swing of 6T and 8T SRAM cell with improved read and write margins

Rawat

Kumar

2021

IJRES

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<span>This article clarifies about the variables that influence the static noise margin (SNM) of a static random-access memory. Track down the improved stability of proposed 8T SRAM cell which is superior to conventional 6T SRAM cell utilizing Swing Restored circuit with voltages Q and QB bar are peruse and Compose activity. This SRAM cell strategy on the circuit or engineering level is needed to improve read static noise margin (RSNM), write static noise margin (WSNM) and hold static noise margin (HSNM). This article relative investigation of conventional 6T, standard 8T and proposed 8T SRAM cells with improved stability and static noise margin is finished for 180 nm CMOS innovation. This paper is coordinated as follows: Introduction in area 1, The 6T SRAM cell are portrayed in segment 2. In area 3, proposed 8T SRAM cell is portrayed. In area 4, standard 8T SRAM cell. Segment 5 incorporates the simulation and results which give examination of different boundaries of 6T and 8T SRAM cells and segment 6 conclusions.</span>

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Section: Hold Stabilitymentioning

confidence: 99%

Restoration circuits for low power reduce swing of 6T and 8T SRAM cell with improved read and write margins

Rawat

Kumar

2021

IJRES

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“…The simulations performed for 180 nm CMOS technology show that there is 3.8% area overhead on comparison with 6T SRAM cell. Another approach to improve the stability of the SRAM cell is to use a 7T read disturbance free differential SRAM cell [24]. This technique isolates the read bit-lines from internal nodes, thereby consuming less energy, but at the cost of area overhead.…”

Section: Related Workmentioning

confidence: 99%

A Novel Approach to Design SRAM Cells for Low Leakage and Improved Stability

Tripathi¹,

Chauhan

Singh³

2018

JLPEA

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The semiconductor electronic industry is advancing at a very fast pace. The size of portable and handheld devices are shrinking day by day and the demand for longer battery backup is also increasing. With these requirements, the leakage power in stand-by mode becomes a critical concern for researchers. In most of these devices, memory is an integral part and its size also scales down as the device size is reduced. So, low power and high speed memory design is a prime concern. Another crucial factor is the stability of static random-access memory (SRAM) cells. This paper combines multi threshold and fingering techniques to propose a modified 6T SRAM cell which has high speed, improved stability and low leakage current in stand-by mode of the memory cell. The simulations are done using the Cadence Virtuoso tool on UMC 55 nm technology.

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“…(1) Obtain Q and QB samples using (2). Figure 6 shows the butterfly curve which is plotted using Q and QB samples for = 0.5V.…”

Section: Quasi MC Sample Generation the Value Of Drv Largely Dependsmentioning

confidence: 99%

“…SRAM plays a major role in random access memory design, but its leakage currents reduction has become a major concern in past decade. Various architectures of SRAM cell have been also proposed in this regard [2,3]. The most straightforward and easier approach for reducing the leakage power is to reduce the supply voltage ( ) of the SRAM cell.…”

Section: Introductionmentioning

confidence: 99%

DRV Evaluation of 6T SRAM Cell Using Efficient Optimization Techniques

Joshi

Nayak

2018

Active and Passive Electronic Components

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An optimization based method which uses bisection search algorithm has been proposed to evaluate the accurate value of Data Retention Voltage (DRV) of a 6T Static Random Access Memory (SRAM) cell using 45 nm technology in the presence of process parameter variations. Further, we incorporate an Artificial Neural Network (ANN) block in our proposed methodology to optimize the simulation run time. The highest values obtained from these two methods are declared as the DRV. We noted an increase in DRV with temperature (T) and process variations (PVs). The main advantage of the proposed technique is to reduce the DRV evaluation time and for our case, we observe improvement in evaluation time of DRV by ≈46, ≈27, and ≈8 times at 25°C for 3 σ, 4 σ, and 5 σ variations, respectively, using ANN block to without using ANN block.

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A read disturbance free differential read SRAM cell for low power and reliable cache in embedded processor

Cited by 23 publications

References 14 publications

Restoration circuits for low power reduce swing of 6T and 8T SRAM cell with improved read and write margins

Restoration circuits for low power reduce swing of 6T and 8T SRAM cell with improved read and write margins

A Novel Approach to Design SRAM Cells for Low Leakage and Improved Stability

DRV Evaluation of 6T SRAM Cell Using Efficient Optimization Techniques

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