A Real-Time Wavelet-Domain Video Denoising Implementation in FPGA

Katona, Mihajlo; Pižurica, Aleksandra; Teslić, Nikola; Kovačević, Vladimir; Philips, Wilfried

doi:10.1186/1687-3963-2006-016035

Cited by 6 publications

(7 citation statements)

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“…In [84], the parallel implementation of an advanced wavelet-domain noise filtering algorithm, which uses a non-decimated wavelet transform and spatially adaptive Bayesian wavelet shrinkage is discussed. The proposed wavelet-domain video denoising algorithm using FPGA is given in Figure 2.15.…”

Section: Hardware Implementation Of Image De-noisingmentioning

confidence: 99%

Efficient reconfigurable architectures for 3D medical image compression

Ahmad

Amira

2009

2009 International Conference on Field-Programmable Technology

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A AbstractRecently, the more widespread use of three-dimensional (3-D) imaging modalities, such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound (US) have generated a massive amount of volumetric data. These have provided an impetus to the development of other applications, in particular telemedicine and teleradiology. In these fields, medical image compression is important since both efficient storage and transmission of data In summary, this research is tackling the issues of massive 3-D medical volumes data that requires compression as well as hardware implementation to accelerate the slowest operations in the system. Results obtained also reveal a significant achievement in terms of the architecture efficiency and applications performance.

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Section: Hardware Implementation Of Image De-noisingmentioning

confidence: 99%

Efficient reconfigurable architectures for 3D medical image compression

Ahmad

Amira

2009

2009 International Conference on Field-Programmable Technology

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“…In a recent paper [16], Katona et al have studied the use of field-programmable gate arrays as a means to implement a real-time wavelet-domain video denoising algorithm. The proposed architecture makes use of two FPGAs.…”

Section: Related Workmentioning

confidence: 99%

Development and Evaluation of High-Performance Decorrelation Algorithms for the Nonalternating 3D Wavelet Transform

Moyano-Ávila

Quiles

Orozco-Barbosa

2007

EURASIP J. Adv. Signal Process.

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We introduce and evaluate the implementations of three parallel video-sequences decorrelation algorithms. The proposed algorithms are based on the nonalternating classic three-dimensional wavelet transform (3D-WT). The parallel implementations of the algorithms are developed and tested on a shared memory system, an SGI origin 3800 supercomputer making use of a messagepassing paradigm. We evaluate and analyze the performance of the implementations in terms of the response time and speed-up factor by varying the number of processors and various video coding parameters. The key points enabling the development of highly efficient implementations rely on the partitioning of the video sequences into groups of frames and a workload distribution strategy supplemented by the use of parallel I/O primitives, for better exploiting the inherent features of the application and computing platform. We also evaluate the effectiveness of our algorithms in terms of the first-order entropy.

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“…Although, each goal taken individually is possible, the set of three is generally beyond the capabilities of traditional design and implementation approaches Villasenor & Mangione-Smith, 1997;Barr, 1998;Ritter & Molitor, 2000;Chrysafis & Ortega, 2000;Lafruit et al, 2000;Russel & Wayne, 2001;Ebrahimi et al, 2002;Nibouche, et al, 2000Nibouche, et al, , 2001aNibouche, et al, , 2001bNibouche, et al, , 2001cNibouche, et al, , 2001dNibouche, et al, , 2002Nibouche, et al, , 2003Katona et al, 2006;Angelopoulou et al, 2008& Lande et al, 2010. Versatile hardware such as general purpose processors (GPP), for example, can perform a wide range of operations and tasks, but fails to reach the system speed of a more specialised hardware.…”

Section: Fpga Implementationmentioning

confidence: 99%

“…Katona et al (Katona et al, 2006) suggest a real time wavelet based video denoising system and its implementation in FPGA. The method adopts a parallel approach to implement an advanced wavelet domain noise filtering algorithm, which uses a non-decimated wavelet transform.…”

Section: Fpga Implementationmentioning

confidence: 99%