A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS

Roshan-Zamir, Ashkan; Elhadidy, Osama; Yang, Hae-Woong; Palermo, Samuel

doi:10.1109/jssc.2017.2705070

Cited by 94 publications

(16 citation statements)

References 24 publications

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“…The feedback signals are connected to the summer through a Gilbert-cell multiplier (M 3∼6 ), whose gain coefficient is controlled by W 1 . Compared to the prior art in [4], [14], it maintains a constant output common mode voltage level of the summer irrespective of its weighting coefficients, which is crucial to the proper operation of the succeeding data slicer. The data slicer for the PAM-4 demodulator is based on a StrongArm latch, as is shown in Fig.…”

Section: B Receiver Front-endmentioning

confidence: 99%

A 32 Gb/s PAM-4 Optical Transceiver With Active Back Termination in 40 nm CMOS Technology

Hsieh

Murmann

et al. 2021

IEEE Open J. Circuits Syst.

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Section: B Receiver Front-endmentioning

confidence: 99%

A 32 Gb/s PAM-4 Optical Transceiver With Active Back Termination in 40 nm CMOS Technology

Hsieh

Murmann

et al. 2021

IEEE Open J. Circuits Syst.

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“…It is known that for NRZ the error propagation of DFE results from the feedback filter can be eliminated effectively by decreasing the tap magnitude and tap number at the cost of equalization performance [15]. In order to maintain the BER performance, FFE with appropriate post-cursor taps can be deployed for PAM4 system to limit the magnitude and number of DFE taps, shown as Fig.…”

Section: Using Tx Ffe For Pam4 Systemmentioning

confidence: 99%

DFE Error Propagation and FEC Interleaving for 400GbE PAM4 Electrical Lane

Zhan

Zhang

2020

IEICE Trans. Electron.

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This paper analyzes the effect of error propagation of decision feedback equalizer (DFE) for PAM4 based 400 Gb/s Ethernet. First, an analytic model for the error propagation is proposed to estimate the probability of different burst error length due to error propagation for PAM4 link system with multi-tap TX FFE (Feed Forward Equalizer) + RX DFE architecture. After calculating the symbol error rate (SER) and bit error rate (BER) based on the probability model, the theoretical analysis about the impact of different equalizer configurations on BER is compared with the simulation results, and then BER performance with FEC (Forward Error Correction) is analyzed to evaluate the effect of DFE error propagation on PAM4 link. Finally, two FEC interleaving schemes, symbol and bit interleaving, are employed in order to reduce BER further and then the theoretical analysis and the simulation result of their performance improvement are also evaluated. Simulation results show that at most 0.52 dB interleaving gain can be achieved compared with non-interleaving scheme just at a little cost in storing memory and latency. And between the two interleaving methods, symbol interleaving performs better compared with the other one from the view of tradeoff between the interleaving gain and the cost and can be applied for 400 Gb/s Ethernet.

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“…lanes [5], [7], a small number of high-speed lanes [6], [9]- [11], re-configurable transceivers [12]- [14], chord signalling (bit-wire encoding) [8], or multi-level signalling schemes [15]. In the simplex standards, except for the Kandou bus where a chord signalling scheme is used, crosstalk is a critical issue affecting signal integrity.…”

Section: Introductionmentioning

confidence: 99%

A 100 Gbps True Full-Duplex Link with Interference Cancellation in the Background

Goyal¹,

Gupta²

2021

Preprint

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In this work, we introduce the concept of true full-duplexing (TFD) for high-speed interconnects. Full-duplex transceivers at the two ends of an interconnect can support simultaneous bidirectional data transfer. Full-duplexing can help in increasing the throughput per lane and also enable higher data transfer bandwidths without an increase in the routing density. The proposed TFD approach allows for the use of independent modulation schemes as well as independent baud-rates by the transceivers on either side of the interconnect. The approach also obviates the requirement of a dedicated start-up protocol or a training sequence for cancellation of near-end interference in the TFD transceivers. In this work, we have used a correlation-based cancellation technique which can support background cancellation of the interference. Here, we demonstrate a 100 Gbps TFD link over a 1 m long coaxial cable with off-the-shelf components, which is the first demonstration of a full-duplex communication link at such a high data rate.

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A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS

Cited by 94 publications

References 24 publications

A 32 Gb/s PAM-4 Optical Transceiver With Active Back Termination in 40 nm CMOS Technology

A 32 Gb/s PAM-4 Optical Transceiver With Active Back Termination in 40 nm CMOS Technology

DFE Error Propagation and FEC Interleaving for 400GbE PAM4 Electrical Lane

A 100 Gbps True Full-Duplex Link with Interference Cancellation in the Background

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