This paper investigates Input/Output Buffer Information Specification Algorithmic Model Interface (IBIS-AMI) model extension for 25Gb/s PAM4 (4-level Pulse Amplitude Modulation) serial link to improve the development efficiency. By using the ADS (Advanced Design System) Channel Simulator, the effects of device package, jitter and crosstalk on the actual performance are studied at first. Then, for forward error correction (FEC) technique, the bit error rate (BER) performance and the bathtub curves are analyzed in detail. Simulation results show that device package, jitter and crosstalk can make the link performance worse. And much better performance can be obtained by using the combination of equalization and FEC techniques compared with using the equalization technique separately.

After the discovery of graphene in 2004, two dimensional (2D) materials have fascinated a lot of view due to the excellent properties. Nowadays, the research on 2D materials has spread to other graphene-like layer structured materials, especially transition metal dichalcogenides (TMDCs). Tin disulfide (SnS2) is a kind of TMDCs with a sizable bandgap. Here we introduce few-layer SnS2 field-effect transistors (FETs) fabricated using micromechanical exfoliation method. The FETs show n-type behavior, the on/off ratio exceeding 0.54×104 and the carrier mobility is 0.61 cm2V−1s−1. The electronic and optical characteristics of SnS2 flakes with a finite bandgap illustrate their potential applications in optoelectronics device.

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This paper analyzes the effect of error propagation of decision feedback equalizer (DFE) for PAM4 based 400 Gb/s Ethernet. First, an analytic model for the error propagation is proposed to estimate the probability of different burst error length due to error propagation for PAM4 link system with multi-tap TX FFE (Feed Forward Equalizer) + RX DFE architecture. After calculating the symbol error rate (SER) and bit error rate (BER) based on the probability model, the theoretical analysis about the impact of different equalizer configurations on BER is compared with the simulation results, and then BER performance with FEC (Forward Error Correction) is analyzed to evaluate the effect of DFE error propagation on PAM4 link. Finally, two FEC interleaving schemes, symbol and bit interleaving, are employed in order to reduce BER further and then the theoretical analysis and the simulation result of their performance improvement are also evaluated. Simulation results show that at most 0.52 dB interleaving gain can be achieved compared with non-interleaving scheme just at a little cost in storing memory and latency. And between the two interleaving methods, symbol interleaving performs better compared with the other one from the view of tradeoff between the interleaving gain and the cost and can be applied for 400 Gb/s Ethernet.

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