A reconfigurable computing platform for real time embedded applications

Say, Fatih; Bazlamaçcı, Cüneyt F.

doi:10.1016/j.micpro.2011.08.013

Cited by 5 publications

(3 citation statements)

References 60 publications

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“…where CT i is the computation time of Task τ i , CC i is task size in terms of Configurable Logic Blocks (CLBs) count [20], T S i is task size in the configuration memory (number of configuration bits), and SB i is the percent of sensitive bits of the task. Any upset in a sensitive bit will eventually affect the functionality of the corresponding task and leads to a failure [21].…”

Section: A Task Modelmentioning

confidence: 99%

Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms

Ramezani

Sedaghat

Naghibzadeh

et al. 2017

IEEE Trans. Aerosp. Electron. Syst.

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Abstract-This paper addresses the problem of reliability and makespan optimization of hardware task graphs in reconfigurable platforms by applying fault tolerance (FT) techniques to the running tasks based on the exploration of the Pareto set of solutions. In the presented solution, in contrast to existing approaches in the literature, task graph scheduling, tasks parallelism, reconfiguration delay, and FT requirements are taken into account altogether. This paper firstly presents a model for hardware task graphs, task prefetch and scheduling, reconfigurable computer and a fault model for reliability. Then, a mathematical model of an integer nonlinear multi-objective optimization problem is presented for improving the FT of hardware task graphs, scheduled in partially reconfigurable platforms. Experimental results show the positive impacts of choosing the FT techniques selected by the proposed solution, which is named Pareto-based. Thus, in comparison to non-fault-tolerant designs or other stateof-the-art FT approaches, without increasing makespan, about 850% Mean Time To Failure (MTTF) improvement is achieved and, without degrading reliability, makespan is improved by 25%. In addition, experiments in fault-varying environments have demonstrated that the presented approach outperforms existing state-of-the-art adaptive FT techniques in terms of both MTTF and makespan.

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Section: A Task Modelmentioning

confidence: 99%

Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms

Ramezani

Sedaghat

Naghibzadeh

et al. 2017

IEEE Trans. Aerosp. Electron. Syst.

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“…These three PHBs, EF, AF, and BE, are handled in a descending priority order. In this paper, we use the reconfigurable computing technique which is a rapidly emerging computing paradigm, not only in research but yet also in real applications due to its superior performance and lower power consumption compared to general purpose computing using microprocessors [5]. Reconfigurable router improves the throughput by changing their packet processing decision to reflect changes in the traffic flow rate.…”

Section: Introductionmentioning

confidence: 99%

Simevents/ Stateflow base Reconfigurable Scheduler in IP Internet Router

AL-Allaf¹

2018

IJCDS

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Quality of Service (QoS) is becoming increasingly important with the rise of multimedia applications (such as voice over IP (VoIP), video conferencing, and so on) in public data networks. These applications demand real-time service, while the networks should still be able to transfer also other traffic reliably (e.g., data, email, and WWW). In this paper, we concern how to improve the QoS of multimedia applications (Voice and video traffic) in DiffServ internet router by using the reconfigurable technique. Therefore we design an QoS model called Reconfigurable Scheduling Model (RSM) for real-time traffic in Diffserv router. In this model, we use the strict priority technique for the voice traffic to reduce the delay and then improve the QoS. While for video traffic, a hardware reconfigurable technique is used to provide the flexibility that improves QoS levels when compared to other techniques such as software-only implementations. This permits the run-time reconfiguration of the router resources, i.e., to change their functionality (from one scheduling algorithm to another), to adapt the fluctuation in traffic parameter. We choose two of the most widely used schedulers (CBWFQ, and MDRR) to support real-time allocations and to improve the QoS of video traffic. The reconfiguration or the switching between those two schedulers is based on queuing delay of the video traffic. To evaluate the proposed approach, the queuing model was built and simulated with MATLAB Simevents and Stateflow components. The result of simulation shows an improvement in QoS of voice and video traffics.

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“…The reason is that, unlike Application-Specific Integrated Circuits (ASICs), FPGAs can be reconfigured multiple times during the mission and also feature lower cost than ASICs, as well as less time to market [2]. Partial reconfigurability makes FPGAs able to configure only a portion of the device while the remaining resources continue their normal operation.…”

Section: Introductionmentioning

confidence: 99%

Reliability Improvement of Hardware Task Graphs via Configuration Early Fetch

Ramezani

Sedaghat

Clemente

2017

IEEE Trans. VLSI Syst.

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Abstract-This study presents a technique to improve the reliability and the Mean Time to Failure (MTTF) of hardware task graphs running on reconfigurable computers. This technique, which has been named Task Early-fetch, can be applied to a sequence of one or several applications, represented as task graphs. It consists in carrying out the reconfiguration of some tasks within the execution of the previous task graph, plus increasing the redundancy level of the early-fetched tasks. Experimental results on actual task graphs show the positive impacts of the proposed technique. Thus, without deteriorating the execution time (makespan), on average, a 114% MTTF improvement is achieved for no-fault-tolerant task graphs, and the improvement is more significant when applying to faulttolerant task graphs. Finally, this paper presents a hardware implementation of a manager that applies these techniques at run-time and steers the execution of the running task graphs. It demonstrates that, with 0.03% consumption of FFs and LUTs and also 1.22% occupancy of BRAMs available on a Xilinx Virtex UltraScale XCVU095-2FFVA2104E FPGA, the required run-time computations can be carried out in negligible delays.

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A reconfigurable computing platform for real time embedded applications

Cited by 5 publications

References 60 publications

Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms

Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms

Simevents/ Stateflow base Reconfigurable Scheduler in IP Internet Router

Reliability Improvement of Hardware Task Graphs via Configuration Early Fetch

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