A reconfigurable cryogenic platform for the classical control of quantum processors

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Ferrari, Giorgio; Prati, Enrico; Foti, Sebastiano; Charbon, Edoardo

doi:10.1063/1.4979611

Cited by 71 publications

(48 citation statements)

References 35 publications

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“…Nevertheless, some commercial CMOS integrated circuits (IC) are functional at cryogenic temperatures, well below their target temperature range. Most notably, some FPGAs remain fully functional down to 4 K with marginal change in operating speed [111], and even DRAM seems functional down to 80 K [112]. The FPGAs could form the basis of a highly reconfigurable cryogenic control platform [94], similar to the current tailor-made controller at room temperature (Section 5.1).…”

Section: Cryogenic Controllersmentioning

confidence: 99%

The electronic interface for quantum processors

Dijk

Charbon

Foti

2019

Microprocessors and Microsystems

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Quantum computers can potentially provide an unprecedented speed-up with respect to traditional computers. However, a significant increase in the number of quantum bits (qubits) and their performance is required to demonstrate such quantum supremacy. While scaling up the underlying quantum processor is extremely challenging, building the electronics required to interface such large-scale processor is just as relevant and arduous. This paper discusses the challenges in designing a scalable electronic interface for quantum processors. To that end, we discuss the requirements dictated by different qubit technologies and present existing implementations of the electronic interface. The limitations in scaling up such state-of-the-art implementations are analyzed, and possible solutions to overcome those hurdles are reviewed. The benefits offered by operating the electronic interface at cryogenic temperatures in close proximity to the low-temperature qubits are discussed. Although several significant challenges must still be faced by researchers in the field of cryogenic control for quantum processors, a cryogenic electronic interface appears the viable solution to enable large-scale quantum computers able to address world-changing computational problems.

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Section: Cryogenic Controllersmentioning

confidence: 99%

The electronic interface for quantum processors

Dijk

Charbon

Foti

2019

Microprocessors and Microsystems

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“…As a classical electronic interface operated at room temperature involves problems such as linearity of interconnections with the number of qubits, linearly scaled thermal flux to the quantum system, and power dissipated to control each qubit before being attenuated of several orders of Quantum information density scaling D Rotta et al magnitude (often 60-100 dB), cryogenic multiplexing in CMOS is being developed. [105][106][107] A generic implementation of a faulttolerant loop is shown in Fig. 3a.…”

Section: Scalable Classical Cmos Control Electronics For Fault-toleramentioning

confidence: 99%

“…The performance observed at cryogenic temperature of the control electronics suggests that three types of multiplexing can be used based on time-division multiple access (TDMA), frequency-division multiple access, and space-division multiple access to significantly reduce the number of interconnects and reduce power dissipation to the cooling power of the refrigerator. The creation of TDMA multiplexers capable of operating at mK temperatures is required, while TDMA demultiplexers and the reminder of the loops can already operate at 1.6-4.2 K. 105,107 The programming of the digital back-end and of the analog front-end can be done with high-speed serial lines, thus minimizing the number of interconnects connecting room temperature devices to cold circuits. In order to minimize the wiring requirements, a first layer of electronic control can be implemented as close as possible to the qubits in terms of temperature and/or physical distance, either on the same silicon substrate or via three-dimensional integration.…”

Section: Scalable Classical Cmos Control Electronics For Fault-toleramentioning

confidence: 99%

Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures

et al. 2017

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Even the quantum simulation of an apparently simple molecule such as Fe 2 S 2 requires a considerable number of qubits of the order of 10 6 , while more complex molecules such as alanine (C 3 H 7 NO 2 ) require about a hundred times more. In order to assess such a multimillion scale of identical qubits and control lines, the silicon platform seems to be one of the most indicated routes as it naturally provides, together with qubit functionalities, the capability of nanometric, serial, and industrial-quality fabrication. The scaling trend of microelectronic devices predicting that computing power would double every 2 years, known as Moore's law, according to the new slope set after the 32-nm node of 2009, suggests that the technology roadmap will achieve the 3-nm manufacturability limit proposed by Kelly around 2020. Today, circuital quantum information processing architectures are predicted to take advantage from the scalability ensured by silicon technology. However, the maximum amount of quantum information per unit surface that can be stored in silicon-based qubits and the consequent space constraints on qubit operations have never been addressed so far. This represents one of the key parameters toward the implementation of quantum error correction for faulttolerant quantum information processing and its dependence on the features of the technology node. The maximum quantum information per unit surface virtually storable and controllable in the compact exchange-only silicon double quantum dot qubit architecture is expressed as a function of the complementary metal-oxide-semiconductor technology node, so the size scale optimizing both physical qubit operation time and quantum error correction requirements is assessed by reviewing the physical and technological constraints. According to the requirements imposed by the quantum error correction method and the constraints given by the typical strength of the exchange coupling, we determine the workable operation frequency range of a silicon complementary metal-oxide-semiconductor quantum processor to be within 1 and 100 GHz. Such constraint limits the feasibility of fault-tolerant quantum information processing with complementary metal-oxide-semiconductor technology only to the most advanced nodes. The compatibility with classical complementary metal-oxide-semiconductor control circuitry is discussed, focusing on the cryogenic complementary metal-oxide-semiconductor operation required to bring the classical controller as close as possible to the quantum processor and to enable interfacing thousands of qubits on the same chip via timedivision, frequency-division, and space-division multiplexing. The operation time range prospected for cryogenic control electronics is found to be compatible with the operation time expected for qubits. By combining the forecast of the development of scaled technology nodes with operation time and classical circuitry constraints, we derive a maximum quantum information density for logical qubits of 2.8 and 4 Mqb/cm 2 for the 10 and 7-...

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“…Spin qubits are being developed by academia [6,7], large pre-industrial fabrication facilities (LETI, IMEC) [8,9], and a large company (Intel). Although the integration of multiple silicon spin qubits with Complementary MetalOxideSemiconductor (CMOS) control electronics is not straightforward, significant steps forward have been done very recently binding the assessment of a full CMOS approach [8] that combines classical electronics with quantum circuits on the same substrate operating at cryogenic temperatures [10,11].…”

Section: Introductionmentioning

confidence: 99%

Is all-electrical silicon quantum computing feasible in the long term?

Ferraro¹,

Prati²

2020

Physics Letters A

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The development of the first generation of commercial quantum computers is based on superconductive qubits and trapped ions respectively. Other technologies such as semiconductor quantum dots, neutral ions and photons could in principle provide an alternative to achieve comparable results in the medium term. It is relevant to evaluate if one or more of them is potentially more effective to address scalability to millions of qubits in the long term, in view of creating a universal quantum computer. We review an all-electrical silicon spin qubit, that is the double quantum dot hybrid qubit, a quantum technology which relies on both solid theoretical grounding on one side, and massive fabrication technology of nanometric scale devices by the existing silicon supply chain on the other.

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A reconfigurable cryogenic platform for the classical control of quantum processors

Cited by 71 publications

References 35 publications

The electronic interface for quantum processors

The electronic interface for quantum processors

Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures

Is all-electrical silicon quantum computing feasible in the long term?

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