A Reconfigurable Platform for Real-Time Embedded Video Image Processing

Sedcole, N. P.; Cheung, Peter Y. K.; Constantinides, George A.; Luk, Wayne

doi:10.1007/978-3-540-45234-8_59

Cited by 26 publications

(17 citation statements)

References 18 publications

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“…N.P. Sedcole et al used such a strategy and built a system for video image processing [25]. A similar method can also be found in the DHP project [14].…”

Section: Proposed Architecturementioning

confidence: 96%

Architecture and operating system support for two-dimensional runtime partial reconfiguration

Wang

Jean

2010

J Supercomput

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Reconfigurable machines based on field programmable gate array (FPGA) chips adapt to applications' needs through hardware reconfiguration. Partial reconfiguration allows the configuration of a portion of a chip while the rest of the chip is busy working on tasks. This paper considers a two-dimensional partially reconfigurable FPGA chip that allows the dynamic swap in and out of circuit modules. Such a chip supports the concurrent execution of multiple applications or an application that is otherwise too large to fit. A challenging issue for 2-D runtime partial reconfiguration is how to support the efficient connection, or routing, between circuit modules or between modules and I/O pins, when those modules may be placed on any area of a chip. Because commercial chips are not efficient in 2-D runtime routing, a new FPGA architecture is proposed based on an array of clusters of configurable logic blocks and a mesh of segmented buses. To evaluate the runtime performance of the architecture, an operating system is specified and implemented which takes care of the scheduling, placement, and routing of circuits on the architecture. Simulation is used to evaluate the efficiency of the OS kernel and to determine the optimal cluster size of the architecture.

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“…N.P. Sedcole et al used such a strategy and built a system for video image processing [25]. A similar method can also be found in the DHP project [14].…”

Section: Proposed Architecturementioning

confidence: 96%

Architecture and operating system support for two-dimensional runtime partial reconfiguration

Wang

Jean

2010

J Supercomput

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“…For these reasons, we are migrating the run-time system to a new database and onto the FPGA itself. Recent work has shown a growing trend for adaptive embedded systems employing run-time self-reconfiguration [2], [12], [13].…”

Section: Sa-tm Video Search Processormentioning

confidence: 99%

Incremental elaboration for run-time reconfigurable hardware designs

Derbyshire

Becker

Luk

2006

Proceedings of the 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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We present a new technique for compiling run-time reconfigurable hardware designs. Run-time reconfigurable embedded systems can deliver promising benefits over implementations in application specific integrated circuits (ASICs) or microprocessors. These systems can often provide substantially more computational power than microprocessors and support higher flexibility than ASICs. The compilation of hardware during run time, however, can add significant runtime overhead to these systems. We introduce a novel compilation technique called incremental elaboration, which enables circuits to be dynamically generated during run time. We propose a set-based model for incremental elaboration, and explain how it can be used in the hardware compilation process. Our approach is illustrated by various designs, particulary those for pattern matching and shape-adaptive template matching.

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“…al. propose a reconfigurable platform for video processing [10]. The design exploits symmetries of the BRAM location in the Virtex-II FPGA to relocate image processing elements.…”

Section: Introductionmentioning

confidence: 99%

Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration

Becker

Luk

Cheung

2007

15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007)

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This paper introduces a method that enhances the relocatability of partial bitstreams for FPGA run-time reconfiguration. Reconfigurable applications usually employ partial bitstreams which are specific to one target region on the FPGA. Previously, techniques have been proposed that allow relocation between identical regions on the FPGA. However, as FPGAs are becoming increasingly heterogeneous, this approach is often too restrictive. We introduce a method that circumvents the problem of having to find fully identical regions based on compatible subsets of resources, enabling flexible placement of relocatable modules. In a software defined radio prototype with two reconfigurable regions, the number of partial bitstreams is reduced by 50% and the compile time is shortened by 43%.

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A Reconfigurable Platform for Real-Time Embedded Video Image Processing

Cited by 26 publications

References 18 publications

Architecture and operating system support for two-dimensional runtime partial reconfiguration

Architecture and operating system support for two-dimensional runtime partial reconfiguration

Incremental elaboration for run-time reconfigurable hardware designs

Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration

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