Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration

Becker, Tobias; Luk, Wayne; Cheung, Peter Y. K.

doi:10.1109/fccm.2007.51

Cited by 69 publications

(42 citation statements)

References 14 publications

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“…This can be used to remove the placement restrictions that stem from the distributed memory feature on Virtex-5. This approach has similarities to [3], where relocatability for modules that possess special resource columns was enhanced by only using the switch matrices of these resources on Xilinx Virtex-4 FPGAs. While in Xilinx Virtex-II FPGAs there exists only one class of special resource columns that provides dedicated multipliers and larger RAM blocks, these resources are available in separate types of columns for dedicated multipliers and memory in the case of a Virtex-5 device.…”

Section: Changes In the Fpga Fabric Layoutmentioning

confidence: 99%

Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs

Koch

Beckhoff

Torrison

2010

2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines

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Abstract-The architecture of Xilinx FPGAs, has changed remarkable with respect to their ability to implement runtime reconfigurable systems throughout the last generations. This paper will discuss these changes and reveal an on-FPGA communication architecture that is especially tailored to Xilinx Virtex-5 FPGAs. With this architecture, modules can be integrated in a two-dimensional grid with more than a hundred of individual tiles while allowing a throughput of several GB/s to reconfigurable modules.

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Section: Changes In the Fpga Fabric Layoutmentioning

confidence: 99%

Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs

Koch

Beckhoff

Torrison

2010

2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines

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“…Other design techniques focus on the relocation between non-identical regions, as [9], however, we decided to only consider relocations between identical regions in the first version of our design flow, as it keeps the floorplanning and regions constraining simpler, even if these techniques could be added in future developments.…”

Section: A Bitstream Relocation On Xilinx Fpgasmentioning

confidence: 99%

AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs

Lalevée

Horrein

Arzel

et al. 2016

2016 Euromicro Conference on Digital System Design (DSD)

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Abstract-Dynamic and partial reconfiguration of Field Programmable Gate Arrays (FPGA) enable to reuse logic resources for several applications which are scheduled in a sequential order or which are loaded on demand. A fraction of the design on the FPGA is then substituted by another logic function while the rest of the system on the chip stays unaffected. If a design provides several partial reconfigurable areas, the configuration bitstream representing the logic function to be configured in this region has to be adapted to the physical requirements of this chip area. This can be achieved by deploying a repository with all possible configuration bitstreams for all possible regions. It is obvious that storage space can quickly become a limiting parameter in reconfigurable designs. For this purpose, bitstream relocation provides a less storage greedy approach. Only one representation as bitstream of an application needs to be stored. During the configuration process, a relocation algorithm manipulates the bitstream in order to suit it to the respective reconfigurable area. However, reconfigurable regions have to fulfill strong constraints for a relocation to be possible, which makes the selection and placement of reconfigurable regions a complex process. Unfortunately this is not automated by tools so far. In this paper, an approach to automate the development of such relocatable bitstreams is presented along with new algorithms related to relocation specific steps. This approach results in functional designs with minimal intervention from the designer.

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“…Finally, the partial configuration data of the PR module is generated, which only targets the tiles of the chosen synthesis region. By manipulating the configuration data as described in [23] and [24], a PR module can be placed at any position with the same arrangement as the types of tiles from which it is built. Therefore, the location and size of the synthesis region defines the set of feasible positions of the PR module as indicated in Fig.…”

Section: Tiled Partially Reconfigurable Systemsmentioning

confidence: 99%

Design Optimizations for Tiled Partially Reconfigurable Systems

Koester

Luk

Hagemeyer

et al. 2011

IEEE Trans. VLSI Syst.

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Abstract-In partially reconfigurable architectures, system components can be dynamically loaded and unloaded allowing resources to be shared over time. Dynamic system components are represented by partial reconfiguration (PR) modules. In comparison to a static system, the design of a partially reconfigurable system requires additional design steps, such as partitioning the device resources into static and dynamic regions. We present the concept of tiled PR regions, which enables a flexible online-placement of PR modules. Dynamic reconfiguration requires a suitable communication infrastructure to interconnect the static and dynamic system components. We present an embedded communication macro, a communication infrastructure that interconnects PR modules in a tiled PR region. Efficient online-placement of PR modules depends not only on the placement algorithm, but also on design-time aspects such as the chosen synthesis regions of the PR modules. We propose a design method for selecting suitable synthesis regions for the PR modules aiming to optimize their placement at run-time.

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Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration

Cited by 69 publications

References 14 publications

Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs

Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs

AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs

Design Optimizations for Tiled Partially Reconfigurable Systems

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