Design Optimizations for Tiled Partially Reconfigurable Systems

Abstract

Abstract-In partially reconfigurable architectures, system components can be dynamically loaded and unloaded allowing resources to be shared over time. Dynamic system components are represented by partial reconfiguration (PR) modules. In comparison to a static system, the design of a partially reconfigurable system requires additional design steps, such as partitioning the device resources into static and dynamic regions. We present the concept of tiled PR regions, which enables a flexible online-placement of PR modules. Dynamic reconfiguration requires a suitable communication infrastructure to interconnect the static and dynamic system components. We present an embedded communication macro, a communication infrastructure that interconnects PR modules in a tiled PR region. Efficient online-placement of PR modules depends not only on the placement algorithm, but also on design-time aspects such as the chosen synthesis regions of the PR modules. We propose a design method for selecting suitable synthesis regions for the PR modules aiming to optimize their placement at run-time.

Dynamic Configuration Prefetching Based on Piecewise Linear Prediction

“…Thus, we simulated each application using the prefetch queues generated by our approach and those generated by [10], [9] and [6]. The parameters for our predictor were chosen, depending on the application size, from the following ranges: α = [0.4, 0.6], q = [2,8], h ∈ [4,16], N ∈ [16,32], M ∈ [8,32].…”

“…We model the PDR region as a matrix of heterogeneous configurable tiles, organized as reconfigurable slots where hardware modules can be placed, similar to [8]. We consider that each hardware candidate has a slot position decided and optimized at design-time using existing methods, such as [5].…”

Energy-aware design of secure multi-mode real-time embedded systems with FPGA co-processors

“…The static region hosts a microprocessor, a reconfiguration controller (that takes care of reconfiguring the PDR region), and potentially other peripheral modules that need not change at run time. The PDR region is organized as reconfigurable slots (composed of heterogeneous configurable tiles), where hardware modules can be reconfigured at run time [10]. We refer to the processor and the PDR region (where the coprocessor resides) as the computation unit (see Fig.…”

Symbolic design space exploration for multi-mode reconfigurable systems

“…An automatic approach to extract possible shapes and positions of such areas for given tasks is presented in [18]. All identified areas are added as partial resources R P R and linked with those communication interfaces lying within the corresponding area.…”

“…We have chosen the publicly available ReCoBus synthesis flow [6] as stateof-the-art technology, since it offers several features: first, communication macros for an on-chip bus which supports We have based the case study on the architecture and results from [20] where we have quantified the performance values, reconfiguration times, and resource requirements of the tasks by analyzing the high-level descriptions in C for software variants, and in VHDL for hardware variants on the implemented architecture. The feasible and efficient allocation areas of the tasks are extracted by using the algorithm presented in [18] to derive minimal synthesis regions, and then determining the feasible positions for found regions. From this specification, we have generated four test-cases which are summarized in Table I.…”