A Reconfigurable Processor Architecture Combining Multi-core and Reconfigurable Processing Unit

Yan, Like; Wu, Binbin; Wen, Yonggang; Zhang, Shaobin; Chen, Tianzhou

doi:10.1109/cit.2010.484

Cited by 11 publications

(10 citation statements)

References 35 publications

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“…To verify the proposed mechanism, we employ the simulation methodology similar to the one used in [5], which was built on top of the Simics platform [4]. The detail of simulation platform is shown in table 1.…”

Section: A Simulation Methodologymentioning

confidence: 99%

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Run-time configuration prefetching to reduce the overhead of dynamically reconfiguration

Yan

Wen

et al. 2010

23rd IEEE International SOC Conference

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Reconfigurable computing is a promising approach with both flexibility and efficiency for high performance computing. However, the overhead of run-time reconfiguration affects the performance severely. In the paper, we develop a simple and effective method to hide the latency of configuration by configuration prefetching at runtime. A simulation platform based on Simics is developed for evaluation. The experimental results show that the predictive accuracy is rather high, the hit rate of reconfigurable processing unit is increased by 24.6%~53.7% when reconfigurable resource is not adequate. I. INTRODUCTIONReconfigurable computing (RC) has been proven to be an effective manner of high performance computing. However, the overhead of run-time reconfiguration affects the performance severely, and becomes one of the main challenges of RC.Configuration prefetching (CP) [2] is proposed to reduce the cost of run-time reconfiguration, but the policy of CP and the strategy combining with scheduling are still challenging.In many previous works, CP is considered to optimize scheduling. Scheduling heuristic at runtime and hybrid design/run-time prefetch heuristic are proposed. Also parallel configuration models are designed with prefetch. However, run-time heuristic scheduling generates an excessive runtime penalty and the hybrid one need design-time preprocesses which is not convenient in practice.This paper proposes a run-time configuration prefetch scheduling to reduce the overhead of dynamically reconfiguration. Without the support of compilers or programmers, predictor can predict the next tasks run-time. According to the predictor, the scheduler can reduce or even eliminate the overhead of run-time reconfiguration and replacements of RPUs will be more reasonable.

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Section: A Simulation Methodologymentioning

confidence: 99%

“…In order to evaluate the run-time configuration prefetch scheduling, the architecture of the system is showed in Fig.1. The basic system architecture called RCM is described in [5]. A prefetcher module is new added to RPU Manager (RPU-M) to prefetch a proper configuration to make RPUs ready to use in advance.…”

Section: Frameworkmentioning

confidence: 99%

Run-time configuration prefetching to reduce the overhead of dynamically reconfiguration

Yan

Wen

et al. 2010

23rd IEEE International SOC Conference

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“…Yan et al present a multi-core architecture that uses a fine-grained reconfigurable fabric in [6]. The fabric is partitioned into reconfigurable processing units (RPUs) of equal size.…”

Section: Related Workmentioning

confidence: 99%

“…allowing non-reconfigurable cores to offload their kernels onto the fabric. Multi-core systems with reconfigurable fabrics have been proposed (such as [5,6,7]), but they do not provide significant utilization improvements compared to a reconfigurable single-core, as (i) they use serialized fabric access, where at a given point in time only one core can access the fabric, (ii) partitioning of the reconfigurable fabric is restricted (e.g. only equal fabric shares for each core), or (iii) the fabric has a very simple structure (e.g.…”

Section: Introductionmentioning

confidence: 99%

Corefab

Grudnitsky

Bauer

Henkel

2014

Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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Application-specific accelerators may provide considerable speedup in single-core systems with a runtime-reconfigurable fabric (for simplicity called "fabric" in the following). A reconfigurable core, i.e. processor core pipeline coupled to a fabric, can be integrated along with regular general purpose processor cores (GPPs) into a reconfigurable multi-core system with widely improved system performance. As most applications only use a fraction of the available fabric at a time, making the fabric usable by the GPPs (in addition to the reconfigurable core) in such a multi-core system is desirable. Existing work focused on algorithms that decide the amount of fabric that is assigned to each core in a multicore system. However, when multiple cores access the fabric simultaneously, they are either limited to serialized fabric access or, when parallel access is supported, the size of the fabric share assigned to a core is inflexible and tends to be over-or undersized for the running application, thereby not efficiently utilizing the fabric. We propose a novel approach that allows GPPs to access the fabric of the reconfigurable core and that enables concurrent fabric utilization on-the-fly through merging fabric accesses from different cores at runtime. Compared to state-of-the art, our approach improves performance of the GPPs in a reconfigurable multi-core system by 1.3× on average, without reducing the performance of the reconfigurable core.

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“…Therefore, it is widely accepted as a single-chip solution for a variety of security scenarios. Many reconfigurable crypto chips were reported [5][6], but very few mentioned SCA resistance.…”

Section: Introductionmentioning

confidence: 98%

A Secure Reconfigurable Crypto IC With Countermeasures Against SPA, DPA, and EMA

Shan

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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IndexTerms-Side-channel attack, Reconfigurable architecture, Cryptographic Coprocessor, correlation based differential analysis (CPA), electromagnetic analysis (EMA).Abstract-A secure reconfigurable cryptographic co-processor (SRCP) supporting multiple algorithms of AES, DES, RC6 and IDEA is proposed using its own reconfigurable feature to resist Side-channel attack (SCA). It is integrated into a system-on chip and fabricated in 0.18 μm CMOS process with 1.8 V supply voltage and 100 MHz max frequency. Several kinds of specific countermeasures are proposed to hide leakage information by utilizing idle reconfigurable processing elements (PEs) to do dummy operations. Its advantages lie in its little impact on area and frequency as well as high flexibility after silicon that countermeasures can also be reconfigured. Furthermore, different protections including several kinds of global countermeasures and encryption flow related countermeasures can be stacked, thus the security level can be tuned by trading for some performance or power consumption. Experimental SCA attack results show that it resists SPA and DPA without revealing the subkey. For correlation based EMA of DES configuration, it increases 36× measure to disclosure when applied with partial countermeasures compared to unprotected DES. As to AES configuration with full countermeasures, it resists EMA with no sign to reveal the right subkey for up to 1.2 million electromagnetic traces.

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A Reconfigurable Processor Architecture Combining Multi-core and Reconfigurable Processing Unit

Cited by 11 publications

References 35 publications

Run-time configuration prefetching to reduce the overhead of dynamically reconfiguration

Run-time configuration prefetching to reduce the overhead of dynamically reconfiguration

Corefab

A Secure Reconfigurable Crypto IC With Countermeasures Against SPA, DPA, and EMA

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