A reconfigurable viterbi decoder for SDR and mobile communications

Abstract

Data rate grows monotonously in every new gen eration of wireless communication system and so does the error rate while transmitting through wireless channels. Hence channel coding, error detection and correction play a major role in overall system performance. Unlike Blockcodes, Convolutional code (CC) offers high error resiliance capacity by increasing their constraint length, instead of increasing the code redundancy. Viterbi de coders have been widely used as the decoder for convolutional codes. In this paper we present a dynamically reconfigurable Viterbi Decoder (VD). The proposed Viterbi decoder supports code rates of 1/2, 1/3,2/3,3/4,5/6, constraint lengths from 3-9, and arbitrary block lengths. The proposed decoder is synthesized in ISE and implemented on Xilinx XCV330T device. A throughput of 197 Mbps is achieved at frequency 197 MHz, which shows the architecture to be superior in terms of reconfiguration and throughput to reconfigurable Viterbi decoders on FPGA platform published in literature.

The design of Viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model

“…A Viterbi decoder convolution code using code rates 1/2, 1/3, 2 /3, 3/4, 5/6, with a constraint length of 3 to 9, and blocks of arbitrary length, has been designed. The proposed decoder has been designed and synthesized using ISE software and implemented using Xilinx XCV330T devices (Pradhan and Nandy, 2014). Prakash and Balamurugan (2015) proposed a 16-PSK by using a convolutional code Viterbi decoder for high-speed data.…”