A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL

Abstract

This article presents a low-power fractional-N alldigital phase-locked loop (ADPLL) employing a referencewaveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, thus leading to lower jitter and settling time. The proposed ROS-PD adopts a bottom-plate sampling with a voltage zero-forcing technique, which yields high power efficiency and supports fractional phase compensation in the voltage domain through a programmable DAC. The PD output is then amplified by a low-noise gated amplifier and digitized by a low-power successive approximation register analog-todigital converter (SAR-ADC). Leveraging the benefits of digital architecture, gain mismatches from the waveform estimator are calibrated by means of an LMS algorithm, consequently lowering fractional spurs. The proposed ADPLL is implemented in TSMC 28-nm LP CMOS. The prototype generates a 2.0-2.3-GHz carrier with an rms jitter of 414 fs while consuming only 1.15 mW. This corresponds to a state-of-the-art ADPLL FoM jitter of −247 dB in a fractional-N mode. Due to the wide (largely linear) monotonic range and 4× oversampling rate from a 50-MHz reference, without any additional circuitry, the proposed ADPLL can settle within 3 µs in face of a 70-MHz frequency step.

Design of Digital Frequency Synthesizer for 5G SDR Systems

“…In [28] developed FPGA based an event-driven all-digital phase locked loop (ADPLL) for asynchronous control. The simulations are carried out using exhaustive test bench to verify individual components of ADPLL networks and statistically comparison with other models in terms of transient response, phase noise and the performance rate.…”

A 3.83–5.55 GHz high frequency resolution DCO with optimized switched‐capacitor ladder and low‐coupled eight‐shaped transformer

“…The ADPLL is more in line with the development trend of semiconductor processes. [1][2][3][4][5][6] As a key module of the ADPLL, the digitally controlled oscillator (DCO) must possess characteristics of high frequency resolution, wide tuning range, and low phase noise to meet the needs of wireless communication systems. Meanwhile, the DCO should realize high insensitivity to interference aspects.…”

“…All‐digital phase‐locked loops (ADPLLs) have outstanding advantages in saving chip area and reducing power consumption since their good programmability, strong anti‐interference ability, and easy integration. The ADPLL is more in line with the development trend of semiconductor processes 1–6 . As a key module of the ADPLL, the digitally controlled oscillator (DCO) must possess characteristics of high frequency resolution, wide tuning range, and low phase noise to meet the needs of wireless communication systems.…”

A Millimeter-Wave ADPLL With Reference Oversampling and Third-Harmonic Extraction Featuring High FoMjitter-N

“…Alternatively, the information contained in the reference sinusoidal XO waveform, S ref , can be extracted by sampling it by the oscillator clock edges [5], [6]. This allows to increase the PD rate, consequently N , by oversampling [7]- [10].…”