A refined forward gated-diode method for separating front channel hot-carrier-stress induced front and back gate interface and oxide traps in SOI NMOSFETs

He, Jin; Zhang, Xing; Huang, Ru; Wang, Yangyuan

doi:10.1088/0268-1242/17/5/314

Cited by 7 publications

(5 citation statements)

References 12 publications

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“…To investigate this possibility we have made gated diode measurements [26,27] on transistors with a large (device a in Fig. 4) and a small (device e in Fig.…”

Section: Short Channel Effects In Filox V-mosfetsmentioning

confidence: 99%

“…A forward bias of 0.4 V was applied between source/drain and body and the gate voltage was swept from À1 V to +1 V. For the pillar top diode subjected to a large over-etch, Fig. 6a shows a significant peak in the diode current (3.2 Â 10 À11 A/lm), which is indicative of the presence of interface states [26,27]. Under a small forward bias (gated diode forward bias voltage, V b < 0.7 V), the diode operates with a contribution from the current in the sub-threshold region and hence the diode current comprises a small diffusion current component but a large SRH generation/recombination current arising from recombination at Si-SiO 2 interface traps.…”

Section: Short Channel Effects In Filox V-mosfetsmentioning

confidence: 99%

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Improved sub-threshold slope in short-channel vertical MOSFETs using FILOX oxidation

Hakim

Tan

Buiu

et al. 2009

Solid-State Electronics

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a b s t r a c tThis paper investigates the origins of sub-threshold slope degradation in vertical MOSFETs (v-MOSFETs) due to dry etching of the polysilicon surround gate. Control v-MOSFETs exhibit a degradation of subthreshold slope as the channel length is reduced from 250 to 100 nm, with 100 nm transistors having a value of 125 mV/dec and a DIBL of 210 mV/V. The effect of the polysilicon gate etch is investigated using a frame-gate architecture in which the polysilicon gate overlaps the side of the pillar, thereby protecting the channel from etch damage. This device shows no degradation of short channel effects when the channel length is scaled and exhibits a near-ideal sub-threshold slope of 76 mV/dec and a DIBL of 33 mV/V at a channel length of 100 nm. Gated diode measurements unambiguously demonstrate that this improved sub-threshold slope is due to the elimination of etch damage at the top and bottom of the pillar created during polysilicon gate etch. An alternative method of eliminating dry etch damage is then investigated by optimizing the Fillet Local Oxidation (FILOX). These devices give a sub-threshold slope of 81 mV/dec and a DIBL of 25 mV/V at a channel length of 100 nm. The improved immunity to dry etch damage is due to the creation of a thick protective oxide at the top and bottom of the pillar during the FILOX process.

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“…To investigate this possibility we have made gated diode measurements [26,27] on transistors with a large (device a in Fig. 4) and a small (device e in Fig.…”

Section: Short Channel Effects In Filox V-mosfetsmentioning

confidence: 99%

Section: Short Channel Effects In Filox V-mosfetsmentioning

confidence: 99%

Improved sub-threshold slope in short-channel vertical MOSFETs using FILOX oxidation

Hakim

Tan

Buiu

et al. 2009

Solid-State Electronics

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“…By comparing the generation rate of the interface states density in FinFET ( N it ∝ t 0.39 ) given by equation (15) with that in SOI MOSFET ( N it ∝ t 0.7 ) [19], the superior of FinFET reliability to the conventional SOI MOSFET is very evident.…”

Section: Analysis Of Interface States and Oxide Trapsmentioning

confidence: 99%

“…In this paper, we performed a detailed study on the degradation of a FinFET using the gated-diode G-R method [12][13][14][15]. It was identified that the degradation is due to two different mechanisms: oxide interface states generation and oxide traps formation.…”

Section: Introductionmentioning

confidence: 99%

FinFET reliability study by forward gated-diode generation–recombination current

Wei

et al. 2008

Semicond. Sci. Technol.

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Reliability of FinFETs is studied in this paper using the forward gated-diode generation-recombination (G-R) current. The current-voltage characteristics of a FinFET are measured for parameter extraction and a mathematical algorithm is used to extract the stress-induced interface states and oxide traps of the FinFET from the G-R current measurement. It is observed that the stress-induced interface states and oxide traps can be distinguished by observing the shift of the peak G-R current in the body current (I b ) versus gate voltage (V g ) characteristic. The interface states cause a change in the maximum G-R current ( I peak ) while the oxide traps result in a shift of the gate voltage ( V g ) corresponding to the I peak . Unlike bulk MOSFETs, the dominant degradation mechanism of FinFETs is found to be the oxide traps formation rather than the interface states generation.

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“…When combined with numerical simulation, the gated-diode method allows the extraction of the lateral distribution of interface traps at the drain-gate overlap regions ( 4 ). The gated-diode approach is also utilized to study carrier generation-recombination at the buried silicon/oxide interfaces of SOI MOSFETs (5,6,7).…”

Section: Introductionmentioning

confidence: 99%

Surface Generation-Recombination Processes of Gate and STI Oxide Interfaces Responsible For Junction Leakage on SOI

Liu¹,

Koldyaev²

2009

ECS Trans.

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Carrier generation-recombination at the top, corner and trench surfaces of silicon-on-insulator (SOI) diode bodies have been studied using the standard gated-diode methodology and new test structures with independent trench-side gates. The influences of top or trench gate voltage, temperature and junction bias have been elucidated. Four distinct diode current peaks are observed during top-gate voltage sweeps. Qualitative analysis has assigned these peaks to surface recombination at the different surface areas of SOI bodies. The coexistence of multiple recombination current peaks might be related to silicon faceting at top trench corners. During top-gate voltage sweeps, STI-gate voltage causes a larger recombination current peak shift for interface traps at the SOI trench corners and walls than those at top SOI interface. A new model involving an oxide trap within the STI oxide has been proposed to interpret the random telegraphic signal (RTS) noise of a gated-diode at high carrier injection and temperature.

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A refined forward gated-diode method for separating front channel hot-carrier-stress induced front and back gate interface and oxide traps in SOI NMOSFETs

Cited by 7 publications

References 12 publications

Improved sub-threshold slope in short-channel vertical MOSFETs using FILOX oxidation

Improved sub-threshold slope in short-channel vertical MOSFETs using FILOX oxidation

FinFET reliability study by forward gated-diode generation–recombination current

Surface Generation-Recombination Processes of Gate and STI Oxide Interfaces Responsible For Junction Leakage on SOI

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