A Region-Based Through-Silicon via Repair Method for Clustered Faults

Ni, Tao; Liang, Hongbin; Nie, Mu; Xu, Xiaodong; Yan, Aibin; Huang, Zhengfeng

doi:10.1587/transele.e100.c.1108

Cited by 13 publications

(10 citation statements)

References 13 publications

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“…To reroute a critical signal, a distant redundant TSV (RTSV) may be used. The additional delay overhead caused by the switch between each TSV and its signal entry can be negligible, and the wire length of rerouting the signal mainly determines the additional delay [4,5,6]. In this case, the additional delay overhead depends on the distances of the original signal TSV and RTSV away from the respect signal entries, which roughly equals the distance between the two TSVs.…”

Section: Metric For Reliabilitymentioning

confidence: 99%

“…Once a TSV is faulty, then all the signals on the repairing paths have to be shifted to the neighboring TSVs. Shifting process continues until the last signals are shifted to RTSVs, and each shifting process will insert extra delay overhead as mentioned in [4,5,6]. The total additional delay overhead should be achieved by summing all the extra delays during signal shifting.…”

Section: Metric For Reliabilitymentioning

confidence: 99%

“…Through silicon vias (TSVs) enable the vertical integration of separate dies to form a single 3D chip. The TSVbased 3D stacking technology promises better performances, including smaller footprint, higher bandwidth, lower power and higher interconnect density [1,2,3,4,5,6,7]. However, the reliability of TSVs may become a serious problem due to electromigration (EM) [1,2,3], which causes TSVs to have voids during field operation.…”

Section: Introductionmentioning

confidence: 99%

“…One promising method to tolerant TSV failure is to add redundant TSVs in the design for built-in-self-repair (BISR). Several TSV redundancy schemes have been proposed [4,5,6,8,9,10]. Kang et al [8] used a signal-switching scheme to improve the yield of 3D DRAM.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A novel in-field TSV repair method for latent faults

Chang

et al. 2018

IEICE Electron. Express

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The aging effect due to the electromigration (EM) may result in faulty Through-silicon vias (TSVs) and affect the three-dimensional integrated circuits (3D ICs) lifetime. To design a flexible and efficient structure, in this paper, we enhance the region-based design for latent TSV faults, which can adjust the size of the TSV block and TSV redundancy. Experimental results demonstrate that the design can achieve 11.27% and 20.79% reduction of additional delay overhead as compared with router-based design and ring-based scheme, respectively. More importantly, when the target year is 3 years, the design can achieve above 99% reparability for all sizes of TSV blocks. After a given 5-year lifetime, the reparability of the proposed regionbased design can still achieve 99% reparability when the TSV size is lower than 16 * 16, which is the best choice by considering RTSV area and delay overhead.

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Section: Metric For Reliabilitymentioning

confidence: 99%

Section: Metric For Reliabilitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A novel in-field TSV repair method for latent faults

Chang

et al. 2018

IEICE Electron. Express

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show abstract

“…Through silicon vias (TSVs) enable the vertical integration of separate dies to form a single 3D chip. The TSVbased 3D stacking technology promises better performances, including smaller footprint, higher bandwidth, lower power and higher interconnect density [1,2]. However, the research on 3DIC from the perspective of hardware security is still relatively few.…”

Section: Introductionmentioning

confidence: 99%

Research on physical unclonable functions circuit based on three dimensional integrated circuit

Chang

Zhang

et al. 2018

IEICE Electron. Express

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As the mainstream technology of the next generation chip design, to ensure the information security of three dimensional integrated circuits (3DIC) is very necessary, however, the existing hardware security technology is still not suitable for 3DIC's unique stack structure and interconnection technology. This paper proposes a novel Physical Unclonable Functions (PUF) circuit technology based on 3DIC. The new scheme exploits the process variation of both CMOS devices and TSVs (Through Silicon Vias) available on TSV-based 3DIC, for secure data generation resistant to physical attacks. In the six layers of the 3DIC, the TSV-based ring oscillator PUF Circuit and independent arbiter PUF circuit are designed. The TSV is introduced as additional sources of process variation, and the same 100 3DIC-PUF chips are simulated through HSPICE under the process variation pre-set. The simulation results show that the TSV-based PUF circuit has good unique and reliability, and can be directly applied to the field of 3DIC security authentication.

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Modelling and analysis of contactless sensor for TSV fault based on resonant inductive coupling

Liu

Chen

et al. 2023

Microelectronics Reliability

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A Region-Based Through-Silicon via Repair Method for Clustered Faults

Cited by 13 publications

References 13 publications

A novel in-field TSV repair method for latent faults

A novel in-field TSV repair method for latent faults

Research on physical unclonable functions circuit based on three dimensional integrated circuit

Modelling and analysis of contactless sensor for TSV fault based on resonant inductive coupling

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